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19-1843; Rev 0; 12/00
MAX1780 Advanced Smart Battery Pack Controller
General Description
The MAX1780 Advanced Battery Pack Controller is a smart battery pack supervisor that integrates a User programmable Microcontroller Core, CoulombCounter-based Fuel Gauge, a multi-channel Data Acquisition Unit, a high-speed SPI Interface, and a Master/Slave SMBus Interface. The 8-bit, RISC, Microcontroller core is user programmable, and provides battery pack designers with complete flexibility in developing fuel gauging and control algorithms. The Data Acquisition Unit can measure individual cell voltages to within 50mV, total battery stack voltage (up to 20.48V), and chip internal/external temperature. The user adjustable overcurrent comparators, along with individual cell voltage measurements, allow the MAX1780 to eliminate a separate primary pack protection IC. The MAX1780 can be directly connected to 2 to 4 series Lithium Ion cells, and supplies itself through a fully integrated 3.4V low drop out linear regulator.
Features
* * * User Programmable Using an External EEPROM Accurate Fuel Gauge Uses V-to-F Method o < 1V Input Offset Voltage o No External Calibration Required Eliminates Separate Primary Protection IC o 50mV Accurate Individual Cell Voltage Measurements o Built in Protection MOSFET Gate Drivers o Over Charge & Discharge Current Protection Fully Integrated LDO (V IN = 4V to 28V) 8-bit RISC Microcontroller Core o On-board 1.5K ROM & 0.5K Program RAM o 144 Bytes Data Memory o Fast Start-up 3.5MHz Instruction Oscillator o Watch Dog Timer Hardware SMBus with Master Capability GPIO Port and High Voltage LED Drivers Typical Operating Currents < 200A Achievable Typical Shutdown Current of 1nA
* *
* * * *
Typical Operating Circuit
+
3.4V DIS SHDN IO4/TIMERA OCI B3P ODI N.C. N.C. CS+ DETECT B2P BATT CHG B4P
Applications
SMBus Battery Packs Proprietary Battery Packs Data Acquisition Systems Remote Data Logging
Pin Configuration
48 47 46 45 44 43 42 41 40 39 38 1 37 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 2 3 4 5
AGND
C D
BATT
B1P SCL
SDA
BN CS+
HV7 HV6 HV5 HV0 HV1 HV2 HV3 OSC2 OSC1 32.768KHz AGND
MAX1780
CS-
6 7 8 9 10 11 12
3.4V
MAX1780ECM
HV4 AIN 3.4V EXTCLK IO6 IO5 IO7/INT1 DISPLAY CAPACITY BTEST BTM0
MCLR
VAA VDD
VCC IO3 IO0/SCLK IO1/SO IO2/SI CS SCLK SI SO VSS WP HOLD
48-PIN TQFP
S
BTM1 BTM2 AGND GND AGND
Ordering Information
PART MAX1780ECM TEMP RANGE -40 C to +85 C PIN/ PACKAGE 48 TQFP
-
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Advanced Smart Battery Pack Controller Table Of Contents
General Description ....................................................................................................................................... 1 Typical Operating Circuit ............................................................................................................................... 1 Features ........................................................................................................................................................ 1 Applications .................................................................................................................................................. 1 Pin Configuration .......................................................................................................................................... 1 Ordering Information ..................................................................................................................................... 1 Table Of Contents.......................................................................................................................................... 2 Table Of Figures............................................................................................................................................ 6 Table Of Tables............................................................................................................................................. 7 List Of Applicable Documents........................................................................................................................ 8 Architectural Overview .................................................................................................................................. 9 Introduction............................................................................................................................................ 9 Harvard Architecture............................................................................................................................... 9 Detailed Description Of MAX1780 ................................................................................................................11 Instruction Execution.................................................................................................................................11 Phase Clocks .............................................................................................................................................12 CPU Architecture ......................................................................................................................................13 Program Counter (PC)............................................................................................................................13 Program Stack .......................................................................................................................................13 Arithmetic Logic Unit (ALU) .................................................................................................................14 Working Register ("W").........................................................................................................................14 Option Register (Write Only, via the "W" Register and OPTION Instruction) ............................................15 Setupint Register (Write Only, via the "W" Register and FREE Instruction) ..............................................16 Memory Organization:...............................................................................................................................17 Page Boundaries ....................................................................................................................................17 Indirect Data Addressing; INDF and FSR Registers..................................................................................18 Register File Organization..........................................................................................................................19 Data RAM.............................................................................................................................................19 File Select Register (FSR) Read/Write.....................................................................................................20 Status Register (Read/Write)...................................................................................................................21 Modes Of Operation ..................................................................................................................................22 Shutdown ..............................................................................................................................................22 Entering Shutdown .............................................................................................................................22 Recovering From Shutdown ................................................................................................................22 Sleep.....................................................................................................................................................22 Entering Sleep Mode ...........................................................................................................................22 Wake-Up From Sleep Mode ................................................................................................................22 Master Clear..........................................................................................................................................22 Operate (Program Execution) ..................................................................................................................22 Analog And Mixed Signal Peripheral Interface............................................................................................23 MAX1780 Power Supply Sequencing .........................................................................................................24 MAX1780 Special Purpose Port Registers...................................................................................................25 PORTA .................................................................................................................................................25 PORTA Data Latch (Read/Write)............................................................................................................25 PORTA TRIS Latch (Write Only) ...........................................................................................................25 PORTB .................................................................................................................................................26 PORTB Data Latch (Read/Write)............................................................................................................27 PORTB TRIS Latch (Write Only) ...........................................................................................................27 Accessing The On-board Peripherals...........................................................................................................27
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Advanced Smart Battery Pack Controller
PORTC (IO0 - IO7)...............................................................................................................................28 PORTC GPIO Operation ........................................................................................................................28 I/O Programming Considerations ............................................................................................................29 PORTC Data Latch................................................................................................................................29 PORTC TRIS Latch...............................................................................................................................29 Timers And Watchdog ...............................................................................................................................30 Timer A (TMRA)...................................................................................................................................30 Timer B (TMRB)...................................................................................................................................30 Watchdog Timer (WDT) ........................................................................................................................31 Interrupts ..................................................................................................................................................32 Description ............................................................................................................................................32 Peripheral Interrupt Control Registers .........................................................................................................33 Interrupt Status Register (INTSTAT) Operation .......................................................................................33 Interrupt Enable Register (INTREN) Operation........................................................................................34 Interrupt Control Register Descriptions....................................................................................................34 Analog Peripherals ....................................................................................................................................35 3.5MHz Instruction Oscillator .................................................................................................................35 32KHz Oscillator ...................................................................................................................................35 Low Drop Out Linear Regulator ..............................................................................................................35 Precision Bandgap Reference..................................................................................................................36 Mixed Signal Peripherals ...............................................................................................................................37 Fuel Gauge Unit ........................................................................................................................................37 General Description ...............................................................................................................................37 Features.................................................................................................................................................37 Automatic Cancellation Of Input Offset Voltage ......................................................................................38 Coulomb Counting .................................................................................................................................38 Charge And Discharge Counters .............................................................................................................38 Current Direction Change Detection Function ..........................................................................................39 Counter Latching Source And Arbiter......................................................................................................39 Direct CPU Control.............................................................................................................................39 ADC Conversion Start and Stop...........................................................................................................40 TIMERA Overflow .............................................................................................................................40 TIMERB Overflow .............................................................................................................................40 Arbitration Logic ................................................................................................................................40 Fuel Gauge Register Descriptions............................................................................................................41 Data Acquisition Unit ...................................................................................................................................43 General Description...................................................................................................................................43 Features....................................................................................................................................................43 Analog Front End/Multiplexer (AFE)..........................................................................................................44 Input Bias Cancellation ..........................................................................................................................44 AFE Register Descriptions ......................................................................................................................45 Analog-To-Digital Converter (ADC) ..........................................................................................................46 Operation ..............................................................................................................................................46 Dual Voltage-To-Frequency Converter....................................................................................................46 Digital Counter/Adder ............................................................................................................................46 Control Logic And Resolution Counter Block..........................................................................................46 Over-Range Status And Limit Bits ..........................................................................................................46 The OVERFLOW Bit .........................................................................................................................46 The SIGN Bit .....................................................................................................................................46 The LIMIT Bit....................................................................................................................................47 Understanding ADC Error Sources..........................................................................................................47
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Advanced Smart Battery Pack Controller
Effective ADC Resolution ......................................................................................................................48 ADC Register Descriptions .....................................................................................................................49 Temperature Sensor ...................................................................................................................................51 Description ............................................................................................................................................51 Operation ..............................................................................................................................................51 Overcurrent Protection Block .....................................................................................................................52 Description ............................................................................................................................................52 DISCHARGE LOGIC.........................................................................................................................53 CHARGE LOGIC...............................................................................................................................53 Using Software To Control The Protection MOSFETs..............................................................................53 Clearing Overcurrent Interrupts...............................................................................................................53 High-Voltage Output Port ..........................................................................................................................55 Description ............................................................................................................................................55 Operation ..............................................................................................................................................56 High-Voltage Output Port Register Description........................................................................................56 Digital Peripherals ........................................................................................................................................57 High-Speed SPI Interface...........................................................................................................................57 Description ............................................................................................................................................57 Operation ..............................................................................................................................................57 SPI Interface Register Descriptions .........................................................................................................58 SMBus Interface........................................................................................................................................59 Introduction...........................................................................................................................................59 Features.................................................................................................................................................59 Description ............................................................................................................................................59 Start Detector .....................................................................................................................................60 Restart Detector..................................................................................................................................60 Stop Detector......................................................................................................................................60 ACK Detector.....................................................................................................................................60 ACK/NACK Generator .......................................................................................................................61 Automatic ACK Generation After a Start or Restart Condition:..............................................................61 Conditional ACK Generation In All Other Slave or Master Mode Receive Operations: ...........................61 SCL Holding Detector.........................................................................................................................61 Automatic SCL Hold Circuit ...............................................................................................................61 Address Comparator ...........................................................................................................................61 Bus Idle Detector ................................................................................................................................61 Master Clock Generator ......................................................................................................................61 35msec Timer.....................................................................................................................................62 Slave Mode Operation ............................................................................................................................62 Initialization .......................................................................................................................................62 Master Mode Operation ..........................................................................................................................62 Sending a START Signal....................................................................................................................63 Sending the Slave Address and Data Direction Bit ................................................................................63 Sending a STOP Signal.......................................................................................................................64 Sending a Repeated START Signal......................................................................................................64 SMBus Interface Register Descriptions....................................................................................................65 Design And Applications Information ............................................................................................................71 Interfacing With An External Serial EEPROM............................................................................................71 Chip Select (CS\) ...................................................................................................................................71 Serial Clock (SCLK) ..............................................................................................................................71 Serial Output (SO) .................................................................................................................................71 Serial Input (SI) .....................................................................................................................................71
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Properly Connecting Lithium Ion Cells .......................................................................................................72 Choosing The Current Sense Resistor (RCS).................................................................................................72 Setting The Overcurrent Thresholds ............................................................................................................73 Handling Battery Insertion Surge Currents ..................................................................................................75 Handling Charger Connection Surge Currents .............................................................................................75 Improving Fuel Gauge Measurement Accuracy...........................................................................................76 Use The Correct Ground Layout .............................................................................................................76 Filter The Current Sense Inputs...............................................................................................................76 Connecting The SHDN Pin ........................................................................................................................77 Shutting Down The MAX1780 Under Software Control ...........................................................................77 Starting Up The MAX1780 After Being Shutdown...................................................................................78 Implementing An SBS-IF Safety Signal......................................................................................................79 Circuit Layout And Grounding ...................................................................................................................79 Pin Descriptions............................................................................................................................................80 Detailed Operating Circuit .............................................................................................................................82 Absolute Maximum Ratings ..........................................................................................................................83 Electrical Characteristics ...............................................................................................................................83 Electrical Characteristics (continued) .............................................................................................................84 Electrical Characteristics (continued) .............................................................................................................85 Electrical Characteristics (continued) .............................................................................................................86 Electrical Characteristics (continued) .............................................................................................................87 SPI Interface Electrical Characteristics...........................................................................................................88 SMBus Interface Electrical Characteristics .....................................................................................................89 Electrical Characteristics (continued, TA = -40C to +85C)............................................................................92 Electrical Characteristics (continued, TA = -40C to +85C)............................................................................93 SPI Interface Electrical Characteristics (TA = -40C to +85C)........................................................................94 SMBus Interface Electrical Characteristics (TA = -40C to +85C)..................................................................95 Typical Operating Characteristics ...............................................................................................................98 Typical Operating Characteristics (continued) .............................................................................................99 Typical Operating Characteristics (continued) ...........................................................................................100 Package Information ...................................................................................................................................102 Appendix ...................................................................................................................................................103 An Overview Of Smart Batteries ..............................................................................................................103 The Smart Battery In A Notebook Power Supply System........................................................................103 What Makes Smart Batteries "Smart"? ..................................................................................................104 Lithium Ion Cell Protection ..................................................................................................................104 Instruction Set Summary..........................................................................................................................105 Errata......................................................................................................................................................107 1. ODO/OCO Section:..........................................................................................................................107 Impact:.............................................................................................................................................107 Solution/Workaround:.......................................................................................................................107 2. ODI/OCI Comparators:.....................................................................................................................107 Impact:.............................................................................................................................................107 Solution/Workaround:.......................................................................................................................107 3. SPI Interface:...................................................................................................................................107 Impact:.............................................................................................................................................107 Solution/Workaround:.......................................................................................................................107 4. SMBus Interface:.............................................................................................................................107 Impact:.............................................................................................................................................107 Solution/Workaround:.......................................................................................................................108
5
Advanced Smart Battery Pack Controller Table Of Figures
Figure 1, MAX1780 Harvard Architecture....................................................................................................... 9 Figure 2, MAX1780 Block Diagram ..............................................................................................................10 Figure 3, MAX1780 Instruction Pipeline ........................................................................................................11 Figure 4, Instruction Cycle Phase Clocks ........................................................................................................12 Figure 5, MAX1780 Programming Model......................................................................................................13 Figure 6, MAX1780 Program Memory Organization.......................................................................................17 Figure 7, DRAM Organization.......................................................................................................................19 Figure 8, MAX1780 On-Board Peripherals .....................................................................................................23 Figure 9, MAX1780 Power Supply Sequencing ..............................................................................................24 Figure 10, PORT B Structure (1 Bit) ..............................................................................................................26 Figure 11, PORTC GPIO Structure (1-Bit) .....................................................................................................28 Figure 12, MAX1780 Timers.........................................................................................................................30 Figure 13, MAX1780 Interrupt Structure........................................................................................................32 Figure 14, Peripheral Interrupt Control Registers ............................................................................................33 Figure 15, Fuel Gauge Block Diagram ...........................................................................................................37 Figure 16, Data Acquisition Unit Block Diagram............................................................................................44 Figure 17, Effective ADC Resolutions............................................................................................................48 Figure 18, Temperature Conversion Bit Weights.............................................................................................51 Figure 19, Overcurrent Comparator Functional Diagram .................................................................................52 Figure 20, High-Voltage Output Port..............................................................................................................55 Figure 21, High-Speed SPI Port.....................................................................................................................57 Figure 22, SMBus Interface Block Dia gram ...................................................................................................60 Figure 23, SMBus Configuration Register ......................................................................................................65 Figure 24, SMBus Status And Mask Registers................................................................................................68 Figure 25, SMBus SLOV Register .................................................................................................................70 Figure 26, External EEPROM Interface Schematic..........................................................................................71 Figure 27, Proper Series Cell Connections ......................................................................................................72 Figure 28, Overcurrent Comparator System Diagram......................................................................................75 Figure 30, Layout Recommendation For Current Sense Inputs.........................................................................76 Figure 31, MAX1780 Software Shutdown Procedure ......................................................................................77 Figure 32, Shutdown Recovery Procedure ......................................................................................................78 Figure 33, MAX1780 Safety Signal Circuit ....................................................................................................79 Figure 34, MAX1780 Application Circuit .......................................................................................................82 Figure 35, SPI Interface Timing .....................................................................................................................88 Figure 36, SMBus Timing Diagram ...............................................................................................................89 Figure 37, SPI Interface Timing (TA = -40C to +85C)..................................................................................94 Figure 38, SMBus Timing Diagram (TA = -40C to +85C) ............................................................................95 Figure 39, Typical ADC Voltage Measurement Error......................................................................................98 Figure 40, SHDN Input Bias Current vs. VSHDN ..............................................................................................99 Figure 41, VAA Output Voltage vs. Load Current and Temperature...................................................................99 Figure 42, Fuel Gauge Frequency vs. Input Voltages Near Zero.....................................................................100 Figure 43, Fuel Gauge Frequency vs. Input Voltage ......................................................................................101 Figure 44, Discharge Gain Error vs. Fuel Gauge Input Voltage ......................................................................101 Figure 45, Charge Gain Error vs. Fuel Gauge Input Voltage ..........................................................................101 Figure 46, Simplified Notebook Computer Power Supply System ..................................................................103 Figure 47, Typical Smart Battery Pack Implemented With The MAX1780 .....................................................104
6
Advanced Smart Battery Pack Controller Table Of Tables
Table 1, Overdischarge Logic Truth Table ......................................................................................................53 Table 2, Overcharge Logic Truth Table ..........................................................................................................53 Table 3, SMBus AC Characteristics ...............................................................................................................91 Table 4, SMBus DC Characteristics ...............................................................................................................91 Table 5, SMBus AC Characteristics (TA = -40C to +85C)............................................................................97 Table 6, SMBus DC Characteristics (TA = -40C to +85C)............................................................................97
7
Advanced Smart Battery Pack Controller List Of Applicable Documents
"System Management Bus Specification", Revision 1.1, dated December 11, 1998. "Smart Battery Data Specification", Revision 1.1, dated December 11, 1998. "MAX1780 ROM Code Supplement", (Contact the Factory for availability) "MAX1780 Programmers Reference Manual", (Contact the Factory for availability)
8
Advanced Smart Battery Pack Controller Architectural Overview
Introduction
The MAX1780 Advanced Smart Battery Pack Controller was designed to provide Smart Battery pack designers with a flexible solution that accurately measures individual cell characteristics. I combines an 8 RISC t -bit microprocessor core, program and data memory, with an arsenal of precision analog peripherals. Together with an external serial EEPROM, the MAX1780 provides the most integrated solution for developing battery pack electronics in the industry.
Harvard Architecture
The MAX1780 uses a Harvard architecture in which program and data are accessed on separate buses. This improves bandwidth over traditional von Neumann architectures where program and data are fetched on the same bus. Separating program and data memory further allows instructions to be sized differently than the 8-bit wide data word. A 12-bit wide program memory bus fetches a 12-bit instruction in a single cycle. The 12-bit wide instruction opcodes make it possible to have all single word instructions.
Program Address (12 bits)
Register Address (8 bits)
Program Memory
Instruction (12 bits)
CPU
Data (8 bits)
SpecialPurpose Registers + Data Memory + Peripherals
Figure 1, MAX1780 Harvard Architecture
The MAX1780 addresses 2K x 12 of internal program memory, organized as three blocks of ROM, each 512 x 12, and one program RAM block 512 x 12. Using special ROM routines (see MAX1780 ROM Supplement for details), the MAX1780 can access up to 64K x 8 of external serial EEPROM memory. This provides software designers with the ability to load program code residing in external EEPROM into program RAM under program control. This innovative capability can be used to develop self-adapting battery management and control software. Figure 2 shows a block diagram of the MAX1780 core microcontroller. MAX1780 memory is organized into program memory and data memory. Program memory pages are accessed using one or two STATUS register bits. Data memory is composed of RAM, organized as 8, 16 byte groups or pages. Collectively, all of the DRAM pages are called the Register File. The register file is divided into two functional groups: special function registers and general purpose registers. DRAM is accessed using the File Selection Register (FSR). The special function registers include the TIMERA Register, the Program Counter (PC), the Status Register, the SETUPINT Register, the I/O registers (ports), and the File Select Register (FSR). In addition, special purpose registers are used to control the I/O port configuration and prescaler options. The General Purpose registers are used for data and control information under command of the instructions. PORTB is used as a dedicated internal interface between the processor core and all the on-board peripherals. Most of the on-board peripherals function autonomously, generating interrupts to the processor core when service is required.
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Advanced Smart Battery Pack Controller
OSC1 OSC2 MCLR\
8-LEVEL STACK
INSTRUCTION OSCILLATOR
32KHz OSCILLATOR
LINEAR REGULATOR
RUN
12
CLK
PROGRAM COUNTER
8
9
PHASE GENERATOR INTERRUPT & SLEEP LOGIC
WATCHDOG TIMEOUT
RESET
12
TIMER B PROGRAM MEMORY ROM (1536x12) RAM (512x12)
TIMER B OVERFLOW
8
3 OPTION REGISTER 8 INTERNAL DATA BUS (8-bits) FROM W REGISTER
INSTRUCTION REGISTER
12
IO4/TMRA
TIMER A CONTROL
TIMER A OVERFLOW
12
5 7 136 x 8 STATIC RAM REGISTER FILE
INSTRUCTION DECODER
LITERALS
TIMER A HIGH BYTE
TIMER A LOW BYTE
FSR
"W" REGISTER
8
8
8
8
INTERNAL DATA BUS (8-bits)
ARITHMATIC LOGIC UNIT
8
8
8
2
PORT A
PORT B
8
PORT C 8
8
8
8
I/O
8
2 2
CONTROL 8 ON-BOARD PERIPHERALS
Figure 2, MAX1780 Block Diagram
10
DATA
INT2&3
ADDRESS
STATUS REGISTER
Advanced Smart Battery Pack Controller Detailed Description Of MAX1780
Instruction Execution
The MAX1780 processor core incorporates a two-stage pipeline. The instruction fetch and execution are pipelined such that an instruction fetch takes one instruction cycle while the instruction decode and execution takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change, for example a GOTO instruction, then two cycles are required to complete the instruction, breaking the pipeline's flow. Figure 3 shows how instruction pipelining increases the processor throughput.
CYCLE 1
CYCLE 2
CYCLE 3
CYCLE 4
Fetch 1 st Instruction
Execute 1 st Instruction
Fetch 2 nd Instruction
Execute 2 nd Instruction
Fetch 3 rd Instruction
Execute 3 rd Instruction
Fetch 4th Instruction
Figure 3, MAX1780 Instruction Pipeline
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Advanced Smart Battery Pack Controller
Phase Clocks
As shown in Figure 4, an Instruction Cycle consists of four phase clocks. The phase clocks do not overlap, and each phase transition occurs on the rising edge of the Instruction Oscillator. Phase 0 (PH0) is called the Decode Phase, where fetched instructions are decoded. Phase 1 (PH1) is known as the Data Read Phase. Any data from Data Memory required to complete the instruction will be read at this time. Phase 2 (PH2) is called the Process Phase, in which any data retrieved in PH1 is processed. The final phase, Phase 3 (PH3), is the Data Write Phase and is used to write data manipulated during PH2 back to Data Memory.
(n - 1)
INSTRUCTION CYCLE (n)
(n + 1)
INSTOSC
PH0
PH1
PH2
PH3
Instruction Decode
Instruction Read Data
Process Data
Instruction Write Data
Figure 4, Instruction Cycle Phase Clocks
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Advanced Smart Battery Pack Controller
Program ROM 0 0x000 - 0x1FF 512 x 12 Program RAM 0x200 - 0x3FF 512 x 12 Program ROM 1 0x400 - 0x5FF 512 x 12 Program ROM 2 0x600 - 0x7FF 512 x 12
12
Program Counter
12
Data Bus
Program Stack 0 Program Stack 1 Program Stack 2 Program Stack 3 Program Stack 4 Program Stack 5 Program Stack 6 Program Stack 7
OPTION Register Data Registers 136 x 8
ADDR
SETUPINT Register Timer A & B Ports A, B, C
MUX
Instruction Register
Instruction Bits [0..7]
FSR Register STATUS Register
DATA Data Bus
DATA
Explicit Data
MUX Instruction Decoder ALU Flags
Z C DC
"W" Register
Figure 5, MAX1780 Programming Model
CPU Architecture
Figure 5 shows the MAX1780's central processing unit (CPU) architecture. As shown, instructions in program memory and variables in data memory are accessed using separate buses
Program Counter (PC)
As a program instruction is executed, the Program Counter (PC) will contain the address of the next program instruction to be executed. The PC value is increased by one every instruction cycle, unless an instruction changes the PC. It should be noted that all subroutine calls are limited to the first 256 locations of any program memory page (512 words long).
Program Stack
The MAX1780 has a 12-bit wide, eight-level hardware stack. This allows program developers to create code with nested subroutine calls. When CALL instructions are executed, pushing the current value onto the stack saves the processor context. A word of caution, the MAX1780 program stack has only 8-levels. Programmers should not create code that has unlimited nesting of subroutine calls, or a stack overflow is possible.
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Advanced Smart Battery Pack Controller
A subroutine call is completed with a RETURN or RETLW instruction, both of which will pop the contents of the stack into the program counter. The RETLW instruction also loads the "W" Register with the literal value specified in the instruction. This is particularly useful for the implementation of data look-up tables within the program memory.
Arithmetic Logic Unit (ALU)
The MAX1780 CPU contains an 8-bit ALU and working register. The ALU is a general-purpose arithmetic unit. It performs arithmetic and Boolean functions between data in the working register and any register file. The ALU is 8-bits wide and capable of addition, subtraction, shift and logic al operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically one operand is the "W" (working) Register. The other operand is either a file register or an immediate constant. In single operand instructions, the operand is either the W Register or a file register. Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register.
Working Register ("W")
The "W" Register serves as an accumulator or temporary storage register for many instructions. The "W" Register is not directly accessible. Its contents must be moved to other registers that are directly accessible, in order to be read. The "W" Register is also used in every arithmetic operation.
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Advanced Smart Battery Pack Controller
Option Register (Write Only, via the "W" Register and OPTION Instruction)
The Option Register is a CPU core register. It is not directly accessible and is not in the Register File address space. To change the contents of the Option Register, use the OPTION instruction, which loads the contents of the "W" Register into the Option Register. Through the Option Register the user has access to the Timer A and Timer B controls. Additionally, whether the Instruction Oscillator runs in SLEEP Mode or not may be selected. Since the contents of the Option Register cannot be read, it is suggested that programmers "shadow" its contents in a global software variable, and all changes be made to the global variable. The global variable is then moved to the "W" Register and an OPTION Instruction executed to affect changes in the Option Register. Bit 7 OSLB
POR STATE
Bit 6
TMRAD
Bit 5 TAS1 1
Bit 4 TAS0 1
Bit 3 MSKW 1
Bit 2 PS2 1
Bit 1 PS1 1
Bit 0 PS0 1
1
1
OSLB 0 1
TMRAD
The Internal Instruction Execution Oscillator Is Turned off During SLEEP Mode. INTOSC OFF in SLEEP. (See note below) The Internal Instruction Execution Oscillator Runs During SLEEP Mode. INTOSC ON in SLEEP.
0 1 TAS1 0 0 1 1 MSKB 0 1
Timer A (TMRA) Enabled Timer A (TMRA) Disabled TAS0 0 1 0 1
TMRA increments count on the falling edge of IO4/TMRA pin TMRA increments count on the rising edge of IO4/TMRA pin TMRA increments count on the rising edge of the 32KHz Clock TMRA increments count on rising edge of INTOSC/4
TIMER B (TMRB) overflow generates an interrupt if INTOFF = 0 (cleared in STATUS Register) TIMER B (TMRB) overflow does not generate an interrupt
PS2 PS1 PS0 0 0 0 TMRB period = (1/32KHz) * 256 * 2 0 0 1 TMRB period = (1/32KHz) * 256 * 4 0 1 0 TMRB period = (1/32KHz) * 256 * 8 0 1 1 TMRB period = (1/32KHz) * 256 * 16 1 0 0 TMRB period = (1/32KHz) * 256 * 32 1 0 1 TMRB period = (1/32KHz) * 256 * 64 1 1 0 TMRB period = (1/32KHz) * 256 * 128 1 1 1 *FACTORY USE ONLY (DO NOT USE) Note: The instruction oscillator will continue to run in SLEEP while an SMBus Slave progress.
15.62 ms 31.25 ms 62.50 ms 125.0 ms 250.0 ms 500.0 ms 1.0 sec transmission is in
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Advanced Smart Battery Pack Controller
Setupint Register (Write Only, via the "W" Register and FREE Instruction)
The Setupint Register is a CPU core register. It is not directly accessible and is not in the Register File address space. To change the contents of the Setupint Register, use the FREE instruction with FSR bits 5 and 6 cleared to `0', which loads the contents of the "W" Register into the Setupint Register. The Setupint Register is used to set-up the triggering characteristics of the MAX1780's three interrupt channels. Additionally, Bit 0 is the global enable bit for addressing the on-board peripherals. Bit 7
SENSE3 POR STATE
Bit 6
SENSE2
Bit 5
SENSE1
Bit 4
EN1SN
Bit 3
EDGE3
Bit 2
EDGE2
Bit 1
EDGE1
Bit 0
PADDR
1
1
1
1
1
1
1
1
Interrupt 3
EDGE3 SENSE3
0 0 1 1
0 1 0 1
IF3 Flag in the PORTA Register is set to `1' when INT3 = `0'. IF3 Flag in the PORTA Register is set to `1' when INT3 = `1'. IF3 Flag in the PORTA Register is set to `1' on a Falling Edge of INT3. IF3 Flag in the PORTA Register is set to `1' on a Rising Edge of INT3.
Note: The Peripheral Interrupt Controller uses INT3 for interrupts. There are total of 8 INT3 interrupt sources: POWER FAILURE, FGCHGSTAT, ADCDONE, DETECT, OCICMP, ODICMP, FGCHGOFL, FGDISOFL.
Interrupt 2
EDGE2 SENSE2
0 0 1 1
0 1 0 1
IF2 Flag in the PORTA Register is set to `1' when INT2 = `0'. IF2 Flag in the PORTA Register is set to `1' when INT2 = `1'. IF2 Flag in the PORTA Register is set to `1' on a Falling Edge of INT2. IF2 Flag in the PORTA Register is set to `1' on a Rising Edge of INT2.
Note: The SMBus Interface uses INT2 for interrupts. There are a total of 7 INT2 interrupt sources: START, RESTART, STOP, SCLHOLD, TOUT, MSTON, ACK.
Interrupt 1
EN1SN EDGE1 SENSE1
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Do not clear the EN1SN bit to `0'. Do not clear the EN1SN bit to `0'. Do not clear the EN1SN bit to `0'. Do not clear the EN1SN bit to `0'. IF1 Flag in the PORTA Register is set to `1' when the IO7/INT1 pin = `0'. IF1 Flag in the PORTA Register is set to `1' when the IO7/INT1 pin = `1'. IF1 Flag in the PORTA Register is set to `1' on an IO7/INT1 Falling Edge. IF1 Flag in the PORTA Register is set to `1' on an IO7/INT1 Rising Edge.
Note: Do not clear the EN1SN bit to `0', otherwise this could result in a constant interrupt from INT1.
Peripheral Address Bit
PADDR D0 This bit must be set to `1' to enable access to on-board peripherals.
Note: This bit defaults to `1' on Power-On -Reset. Do not change or the on-board peripherals cannot be addressed.
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Advanced Smart Battery Pack Controller
Memory Organization:
The MAX1780 program memory is divided into four blocks 512 x 12-bits in size. Each block is further divided into 256 x 12-bits upper and lower pages. The first, third, and fourth blocks are Program ROM, which are programmed at the factory. The second memory block is Program RAM, which is loaded with user code at boot, and can be modified during operation.
0x000 PROGRAM ROM 0 LOWER PAGE 0x0FF 0x100 PROGRAM ROM 0 UPPER PAGE 0x1FF 0x200 PROGRAM RAM LOWER PAGE 0x2FF 0x300 PROGRAM RAM UPPER PAGE 0x3FF 0x400 PROGRAM ROM 1 LOWER PAGE 0x4FF 0x500 PROGRAM ROM 1 UPPER PAGE 0x5FF 0x600 PROGRAM ROM 2 LOWER PAGE 0x6FF 0x700 PROGRAM ROM 2 UPPER PAGE 0x7FF
Figure 6, MAX1780 Program Memory Organization
Page Boundaries
The Page Preselect bits (PA0 - PA1) of the STATUS Register determine which 512 x 12 page of program memory the MAX1780 CPU fetches instructions from. They are mapped as:
Program Memory Selection:
PA2 X X X X PA1 0 0 1 1 PA0 0 1 0 1 Address Range 0x000 - 0x1FF 0x200 - 0x3FF 0x400 - 0x5FF 0x600 - 0x7FF Memory Selected ROM (512 WORDS) RAM (512 WORDS) ROM (512 WORDS) ROM (512 WORDS)
Each instruction cycle causes the Program Counter to increment, which in turn, increments the address in program memory from where instructions are fetched. Program flow within a 512 x 12 page is controlled by GOTO and CALL instructions. GOTO instructions provide 9 bits of address for the Program Counter, so program control can be transferred to any memory address within a page. The CALL instruction on the other
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Advanced Smart Battery Pack Controller
hand, supplies the Program Counter with only 8 bits of address. This limits jumps by the CALL instruction to the lower half of the memory page selected by the Page Preselect Bits (PA0 - PA1). The Page Preselect Bits have no effect on program flow until a CALL or a GOTO instruction is executed. If the Program Counter is pointing to the last address of a selected memory page, when it increments it will cause the program to continue in the next higher page. However, the Page Preselect bits in the STATUS register will not be updated. Therefore, the next GOTO or CALL instruction will send the program to the page specified by the Page Preselect bits (PA1:PA0). For example, a NOP at location 1FFh (page 0) increments the PC to 200h (page 1). A GOTO xxx at 200h will return the program to address 0xxh on page 0 (assuming that PA1:PA0 are clear). To prevent this, the page presele ct bits must be updated under program control.
Indirect Data Addressing; INDF and FSR Registers
The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing. The FSR is an 8-bit wide register. It is used in conjunction with the INDF register to indirectly address the data memory area. The FSR [4:0] bits are used to select data memory addresses 0x00 to 0x1F.
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Advanced Smart Battery Pack Controller
Register File Organization
Data RAM
The MAX1780 has 144 bytes of read/writable Data Memory. It is organized as follows: 8 8 128 Special Purpose Register Files (Page Independent) General Purpose Registers (Page Independent) General Purpose Registers (Page Dependent)
The FSR Register (bits 5 - 7) is used to select the desired data memory block. As shown in Figure 7 below, the special purpose registers and first 8 general purpose registers (0x00 - 0x0F) are shadowed across all eight Data RAM blocks. For this reason, the contents of these registers are accessible regardless of which memory block is selected by FSR bits 5 - 7. Data stored in this area is referred to as "Page Independent" memory. Selecting the appropriate FSR bits allow access to data residing in the upper 16 bytes of each block. Data stored in this area is referred to as "Page Dependent" memory.
FSR [ 7:5 ]
000
0x00 INDF 0x20
001
INDF 0x40
010
INDF 0x60
011
INDF 0x80
100
INDF TIMERA (LB) PC STATUS FSR PORTA PORTB PORTC 0xA0
101
INDF 0xC0
110
INDF 0xE0
111
INDF
TIMERA (LB) PC STATUS FSR PORTA PORTB PORTC 0x08 GPR (8 Bytes) 0x0F 0x10
TIMERA (HB) PC STATUS FSR PORTA PORTB PORTC
TIMERA (LB) PC STATUS FSR PORTA PORTB PORTC
TIMERA (HB) PC STATUS FSR PORTA PORTB PORTC
TIMERA (HB) PC STATUS FSR PORTA PORTB PORTC
TIMERA (LB) PC STATUS FSR PORTA PORTB PORTC
TIMERA (HB) PC STATUS FSR PORTA PORTB PORTC
GPR (8 Bytes) 0x2F 0x30 0x4F 0x50
GPR (8 Bytes) 0x6F 0x70
GPR (8 Bytes) 0x8F 0x90
GPR (8 Bytes) 0xAF 0xB0
GPR (8 Bytes) 0xCF 0xD0
GPR (8 Bytes) 0xEF 0xF0
GPR (8 Bytes)
GPR (16 Bytes)
GPR (16 Bytes)
GPR (16 Bytes)
GPR (16 Bytes)
GPR (16 Bytes)
GPR (16 Bytes)
GPR (16 Bytes)
GPR (16 Bytes)
0x1F
0x3F
0x5F
0x7F
0x9F
0xBF
0xDF
0xFF
BLOCK 0
BLOCK 1
BLOCK 2
BLOCK 3
BLOCK 4
BLOCK 5
BLOCK 6
BLOCK 7
Figure 7, DRAM Organization
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Advanced Smart Battery Pack Controller
File Select Register (FSR) Read/Write
The File Select Register selects which page of Data Memory can be accessed. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR STATE
X Bit6 0 0 1 1 0 0 1 1 Bit5 0 1 0 1 0 1 0 1
X
X
X
X
X
X
X
Bit7 0 0 0 0 1 1 1 1 Bit4 0
GPR SELECTED GPR Page/Block 0 - TIMERA Low Byte selected. GPR Page/Block 1 - TIMERA High Byte selected. GPR Page/Block 2 - TIMERA Low Byte selected. GPR Page/Block 3 - TIMERA High Byte selected. GPR Page/Block 4 - TIMERA Low Byte selected. GPR Page/Block 5 - TIMERA High Byte selected. GPR Page/Block 6 - TIMERA Low Byte selected. GPR Page/Block 7 - TIMERA High Byte selected.
Page Independent/Dependent Selection Page independent Data Memory (lower 16 bytes of each Page/Block) is accessed. The lower 16 bytes of Page/Block 0 are shadowed across the other 7 page/blocks regardless of the selection of FSR bits 5 - 7. 1 Page dependent Data Memory (upper 16 bytes of each Page/Block) is accessed. Selecting bits 5 - 7 of the FSR accesses a Page/Block. Selecting FSR bits 0 - 3, accesses individual bytes within a Page/Block. Selection of Register File or Data RAM Bit3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Data RAM Location 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F
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Advanced Smart Battery Pack Controller
Status Register (Read/Write)
The Status Register contains the arithmetic status of the ALU, TMRB overflow status, the global interrupt enable/disable bit, and the Page Preselect bits for selecting from which page of program memory program code will be fetched. The Status Register can be the destination for any instruction. If the Status Register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. It is recommended, therefore, that only BCF, BSF and MOVWF instructions be used to alter the STATUS register because these instructions do not affect the Z, DC or C bits from the STATUS register. Bit 7 PA2
POR STATE
Bit 6 PA1 0
Bit 5 PA0 0
Bit 4
TMRBF
Bit 3
INTOFF
Bit 2 Z X Type ROM RAM ROM ROM
Bit 1 DC X
Bit 0 C X
0
0
1
PA2 PA1 PA0 Memory Range Selected X 0 0 0x000 - 0x1FF X 0 1 0x200 - 0x3FF X 1 0 0x400 - 0x5FF X 1 1 0x600 - 0x7FF Note: PA2 is not implemented but can be used as storage. TMRBF 0 1 TIMER B overflow flag CLEARED TIMER B overflow flag SET
Length 512 WORDS 512 WORDS 512 WORDS 512 WORDS
INTOFF 0 Enable Global Interrupts 1 Disable Global Interrupts Z 0 1
Arithmetic or Logic Operation Results is NOT Zero Arithmetic or Logic Operation Results is Zero
DC 0 No CARRY from Bit3 to Bit4 1 CARRY from Bit3 to Bit4 Note: Effected only by ADDWF & SUBWF Instructions C 0 1 No CARRY from Bit7 (MSB). When no CARRY generated in Addition, or when subtraction result is negative. CARRY from Bit7 (MSB). When CARRY is generated in Addition, or when subtraction result is zero or positive.
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Advanced Smart Battery Pack Controller
Modes Of Operation
The MAX1780 has four modes of operation: 1. Shutdown ( SHDN = Low) 2. Sleep 3. Master Clear (MCLR = Low) 4. Operate (Program Execution)
Shutdown
In shutdown mode, the MAX1780 consumes practically no current. This mode is useful for reducing the selfdischarge of battery packs in transit to customers or being stored for long periods.
Entering Shutdown
To enter shutdown mode, the SHDN pin should be grounded. When the voltage on the SHDN pin falls below 0.4V, the MAX1780 will enter a very low power (typically 1nA) consumption mode.
Recovering From Shutdown
To recover from shutdown mode, the SHDN pin should be connected to the BATT pin through a 3Megohm resistor. After the voltage at the SHDN pin has risen to a level greater than 2.2V, the MAX1780 will Power On Reset (POR) and begin to execute code.
Sleep
In sleep mode, instruction execution is suspended. The internal instruction oscillator may be on or off in sleep mode depending on the contents of the OSLB bit (D7) of the Option Register. The internal instruction oscillator turns on whenever sleep mode is exited regardless of the condition of the OSLB bit.
Entering Sleep Mode
Executing a SLEEP instruction enters sleep Mode.
Wake-Up From Sleep Mode
The MAX1780 can wake up from SLEEP through one of the following events: 1. An external reset input on the MCLR pin. 2. A Watchdog time-out. 3. An interrupt from any enabled source will wake up the MAX1780, regardless of the state of the INTOFF bit in the STATUS Register.
Master Clear
Placing a logic level LOW on the MCLR pin will cause the MAX1780 to reset all its internal logic circuitry. While MCLR is LOW all program execution is halted. Additionally, all GPIO pins are high-impedance, and the CHG and DIS pin drivers will rise to VBATT, opening both pack protection MOSFETs. Releasing the logic LOW on the MCLR pin, allowing it to rise to VDD, will allow the processor core to boot and begin program execution.
Operate (Program Execution)
Whenever instructions are executing, the MAX1780 is in operate mode.
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Analog And Mixed Signal Peripheral Interface
The MAX1780 integrates an arsenal of analog and mixed signal peripheral devices. The processor core communicates with these on-board peripherals through PORT B, as shown in Figure 8.
PORT A PORT B
INT3 FROM CPU CORE
INT 2
ADDRESS
8
DATA
ODI
8
READ WRITE REF OUT READ WRITE OSCD4 MCLR PFW TIMERA_OVFL INT OCI
ODI/OCI COMPARATORS
+
ANALOG REFERENCE
DIS
ADDRESS
8
DATA
8
CHG
OUT
ADDRESS
ADDRESS
8
DATA
8
DATA B4P
8
READ WRITE
8
READ WRITE OSCD4 MCLR PFW TIMERA_OVFL INT
INTERRUPT CONTROL REGISTER
OSCD4 MCLR PFW
DATA ACQUISITION UNIT
B3P
B2P
B1P
INTERRUPTS
ADDRESS
CONTROL
BN
INT0 - INT7
DATA
ADDRESS
8
DATA
8
READ WRITE READ WRITE OSCD4 MCLR CS+
FUEL GAUGE
HIGH VOLTAGE OUTPUT HV[0..7] PORT
PFW TIMERA_OVFL CSINT AGND
-
ADDRESS
8
DATA
8
ADDRESS
ADDRESS
8
DATA
8
DATA
8
READ SCLK SPI WRITE SO INTERFACE SI OSCD4 MCLR PFW
8
READ WRITE OSCD4 MCLR PFW TIMERA_OVFL INT
SMBus INTERFACE
SCL SDA
C D
Figure 8, MAX1780 On-Board Peripherals
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Advanced Smart Battery Pack Controller
MAX1780 Power Supply Sequencing
The MAX1780 incorporates both analog and digital circuitry, which each have an optimal power supply range. The digital circuitry can begin operating with VAA voltages as low as 2.7V, whereas the analog circuitry begins to operate at 3.0V. This means that the MAX1780 CPU can begin executing program code before it's analog peripherals have powered up. The MAX1780 uses two internal control signals, POR for the digital circuitry, and PFW for the analog circuitry, to determine if the VAA supply has reached a voltage level high enough for both the digital and analog circuitry to operate. Figure 9 illustrates the MAX1780 power supply sequencing.
3.6 3.5 3.4 3.3
OPERATION
VAA (Volts)
3.2 3.1 3.0
INTERRUPT
2.8 2.7 2.6 2.5
RA M PU P
2.9
INTERRUPT
RA MP DO W N
POR
PFW
Digital Supply Turns ON
Analog Supply Turns ON
Analog Supply Turns OFF
Digital Supply Turns OFF
Figure 9, MAX1780 Power Supply Sequencing
Whenever the VAA supply rises above, or falls below 3.0V an interrupt is generated. Please refer to the Peripheral Interrupt Control Register section for a detailed description of this interrupt. Immediately after power-up, the interrupt can be used to indicate that both the digital and analog supplies have reached a reliable voltage level for operation. Any interrupts that occur after the initial power-up sequence, could be an indication that the VAA supply has either momentarily fallen below 3.0V, or is powering off.
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Advanced Smart Battery Pack Controller
MAX1780 Special Purpose Port Registers
Each port line can be individually programmed as an input or output. This is done by using a special purpose instruction TRIS, which matches a bit pattern with the port lines. Writing a `0' to a port line's TRIS Register configures this port line as an output. Conversely, setting a port line's TRIS Register to `1' configures the port line as an input.
PORTA
The MAX1780 PORTA[3:0] signal lines are not connected to external pins. The PORTA data latch is however read/writable, so bits 0 - 3 can be freely used as storage.
PORTA Data Latch (Read/Write)
Bit 7 IF3
POR STATE
Bit 6 IF2 0
Bit 5 IF1 0
Bit 4
TMRAF
Bit 3
PORTA3
Bit 2
PORTA2
Bit 1
PORTA1
Bit 0
PORTA0
0
0
1
1
1
1
IF3, IF2, IF1 are the Interrupt Flags for INT3, INT2, INT1 respectively. They will be set whenever there is a respective interrupt. TMRAF flag is set when there is a TIMERA overflow.
PORTA TRIS Latch (Write Only)
Bit 7 MA3
POR STATE
Bit 6 MA2 1
Bit 5 MA1 1
Bit 4
MTMRA
Bit 3
X
Bit 2
X
Bit 1
X
Bit 0
X
1
1
1
1
1
1
MA3, MA2, MA1, MTMRA are the interrupts of INT3, INT2, INT1, TIMERA Enable Control. Writing a `0' to an individual bit will enable the respective interrupt.
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Advanced Smart Battery Pack Controller
PORTB
PORTB is a special purpose port used to communicate with the on-chip peripherals. The address for a desired peripheral is written to the PORTB TRIS Latch, and the data is either written to or read from the PORTB Data Latch using a MOVF instruction. Care should be taken to properly protect Main Loop PORTB peripheral transactions from interrupt service routines that may also use PORT to communicate to peripherals.
RESET
D
TRIS PORTB
SET
PERIPHERAL ADDRESS
Q
CLR
Q
VDD
I/O CONTROL LATCH "W" REGISTER
P D 7 D 6 D5 D4 D3 D2 D1 D0
INTERNAL DATA BUS
P PERIPHERAL DATA
ON-BOARD PERIPHERAL
MOVF PORTB, 0 PERIPHERAL READ
N
RD\ WR\
D
MOVF PORTB, 1 PERIPHERAL WRITE
SET
Q
CLR
Q
N
OUTPUT DATA LATCH
GND
Figure 10, PORT B Structure (1 Bit)
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Advanced Smart Battery Pack Controller
PORTB Data Latch (Read/Write)
Bit 7 D7
POR STATE
Bit 6 D6 1
Bit 5 D5 1
Bit 4 D4 1
Bit 3 D3 1
Bit 2 D2 1
Bit 1 D1 1
Bit 0 D0 1
1
PORTB TRIS Latch (Write Only)
Bit 7 A7
POR STATE
Bit 6 A6 1
Bit 5 A5 1
Bit 4 A4 1
Bit 3 A3 1
Bit 2 A2 1
Bit 1 A1 1
Bit 0 A0 1
1
Accessing The On-board Peripherals
The MAX1780 processor core can access on-board peripherals provided that the Setupint Register PADDR bit D0 is set to `1'. The peripheral's address is first written to the PORT B TRIS latch. If a peripheral read is desired, then a MOVF instruction is executed to latch the peripheral bus data into the "W" Register. If a peripheral write is wished, then in addition to writing the peripheral's address to the PORT B TRIS latch, the data for the peripheral must be written to the PORT B DATA latch. The following code example shows how to read data from an on-board peripheral using the PORT B internal interface. Peripheral Read MOVLW ADDRESS TRIS Port_B MOVF Port_B,0 Load the peripheral's address in W register. Latches the address. Generates Read signal and returns peripheral INPUT data to the W register.
Programming code for write operations is similar, except that two extra move instructions are required to latch the data sent to the PORT B peripheral. Peripheral Write MOVLW TRIS MOVLW MOVWF MOVF ADDRESS Port_B DATA Port_B Port_B,1 Load the peripheral's address in W register. Latches the address. Load Peripheral's data in W register. Puts Data Into B For Output. Generates Write signal and sends OUTPUT data to the peripheral.
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Advanced Smart Battery Pack Controller
PORTC (IO0 - IO7)
Port C shares duty as a general-purpose I/O (GPIO) port and SPI interface. Bits IO0, IO1, and IO2 are used exclusively in normal operation by the high-speed SPI interface. Bit IO3, under software control, is used for the SPI CS\ signal. Bit IO4, when configured as an input, can be used to increment Timer A. Bit IO7 shares use as an external input to the INT1 interrupt. Bits IO5 and IO6 are free GPIOs.
"W" REGISTER D7 D6 D5 D 4 D3 D2 D1 D0
VDD
D
PORTC WRITE
SET
Q
CLR
Q
P
INTERNAL DATA BUS
DATA LATCH I/O PIN
D
TRIS PORTC
SET
Q
N
CLR
Q
TRIS LATCH PORTC READ GND
Figure 11, PORTC GPIO Structure (1-Bit)
PORTC GPIO Operation
The equivalent circuit for one of the PORTC GPIO port pins is shown in Figure 11. PORTC, IO0 - IO7 may be used for both input and output operations. For input operations PORTC is non-latching. Any input must be present until read by an input instruction (e.g., MOVF PORTC, W). The outputs are latched and remain unchanged until the output latch is rewritten. To use a PORTC I/O pin as output, the corresponding direction control bit in TRIS latch must be cleared. For use as an input, the corresponding TRIS bit must be set. Any I/O pin can be programmed individually as input or output. The TRIS latch is loaded with the contents of the "W" Register by executing the TRIS f instruction. A '1' from a TRIS register bit puts the corresponding output driver in a hi-impedance mode. A '0' puts the contents of the output data latch on the selected pins, enabling the output buffer. The TRIS registers are "write-only" and are set (output drivers disabled) upon RESET.
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Advanced Smart Battery Pack Controller
Note: A read of the ports reads the pins, not the output data latches. That is, if an output driver on a pin is enabled and driven high, but the external system is holding it low, a read of the port will indicate that the pin is low. At power-on-reset, all port lines are tri-stated. All unused port lines should be tied to VDD. Please refer to the MAX1780 Electrical Characteristics and Absolute Maximum Ratings when connecting the I/O port lines to external circuitry.
I/O Programming Considerations
Some instructions operate internally as read followed by write operations. The BCF and BSF instructions, for example, read the entire port into the CPU, execute the bit operation and re-write the result. Caution must be used when these instructions are applied to a port where one or more pins are used as input/outputs. For example, a BSF operation on bit-7 of PORTC will cause all eight bits of PORTC to be read into the CPU, bit-7 to be set and the PORTC value to be written to the output latches. If another bit of PORTC is used as a bidirectional I/O pin (say bit0) and it is defined as an input at this time, the input signal present on the pin itself would be read into the CPU and rewritten to the data latch of this particular pin, overwriting the previous content. For this reason, it is good programming practice to "shadow" the PORTC data latch. This involves maintaining a copy of the PORTC data latch contents in a data RAM location. Individual bits are set by first "OR-ing" the desired bits with the PORTC data latch copy, and then moving the latch copy to the PORTC latch. Likewise, individual port bits can be cleared by "AND-ing" the reciprocal of the desired bits with the PORTC data latch copy, followed by a move to the data latch.
PORTC Data Latch
Bit 7 IO7 INT1
POR STATE
Bit 6 IO6 1
Bit 5 IO5 1
Bit 4 IO4/ TMRA 1
Bit 3 IO3 (CS\) 1
Bit 2 IO2/ SI 1
Bit 1 IO1/ SO 1
Bit 0 IO0/ SCLK 1
1
PORTC TRIS Latch
Bit 7 TRIS7
POR STATE
Bit 6 TRIS6 1
Bit 5 TRIS5 1
Bit 4 TRIS4 1
Bit 3 TRIS3 1
Bit 2 TRIS2 1
Bit 1 TRIS1 1
Bit 0 TRIS0 1
1
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Advanced Smart Battery Pack Controller
Timers And Watchdog
Figure 12 below shows the organization of Timer A, Timer B, and the Watchdog Timeout circuitry.
8
"W" REGISTER
8
OPTION COMMAND
OPTION REGISTER D6 D5 D4 D3 D2 D1 D0
Mask
PRESCALER
INTERNAL DATA BUS (8-Bits)
TMRB OVERFLOW
1sec
2sec WATCHDOG TIMEOUT
D
Q
D
Q
FF
CLK
FF
Q Reset
TIMER B (15-Bits)
Q Reset
CLRWDT 32KHz IO4/TMRA IO4/TMRA INTOSC/4 FSR Bit 5
HB/LB Select
MUX
CLK
Start/Stop
TIMER A (16-Bits)
TMRA OVERFLOW
8
8 8 REGISTER SELECT
TIMER A REGISTER (HB)
8
TIMER A REGISTER (LB)
Figure 12, MAX1780 Timers
Timer A (TMRA)
TMRA is a general-purpose 16-bit ripple counter that can be configured to use one of four clock sources, IO4/TMRA pin rising edge, IO4/TMRA pin falling edge, 32KHz oscillator rising edge, or the rising edge of the instruction oscillator divided by four. Setting the TAS0 and TAS1 bits in the Option Register selects the clock source. When either the 32KHz oscillator or IO4/TMRA pin clock the timer, the timer operates asynchronously of the MAX1780 processor core. This means that the timer can count events even when the CPU core is in sleep mode, as it does not need the instruction oscillator to count. The user can enable Timer A by clearing the TMRAD bit in the Option Register. To disable Timer A, set the TMRAD bit in the Option Register. When TMRA overflows, the ITMRA flag in the Status Register is set and an interrupt will be generated. This flag should be cleared by the TMRA interrupt service routine. If the MAX1780 CPU is in SLEEP mode when a TMRA overflow occurs, it will wake-up the CPU.
Timer B (TMRB)
Timer B is a 15-bit ripple counter permanently attached to the 32KHz crystal oscillator. It has a 3-bit prescaler to divide the oscillator down to obtain timer periods between 15.625msec and 1sec. The prescaler can be adjusted by writing to bits PS0 through PS2 in the Option Register and executing an OPTION instruction. If the MSKB bit in the Option Register is cleared, each time the TMRB period is exceeded (overflows), an interrupt is generated and the TMRBF flag in the Status Register is set. The TMRB interrupt service routine should first,
30
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Advanced Smart Battery Pack Controller
execute a CLRTI instruction and then clear the TMRBF flag. If the MAX1780 CPU is in SLEEP mode when a TMRB overflow occurs, it will wake-up the CPU. TMRB is a logical choice for creating an accurate real-time clock that generates recurring interrupts at a desired period.
Watchdog Timer (WDT)
The primary function of the Watchdog Timer is to be a failsafe method for recovering from programs that are stuck in an endless loop, or may have inadvertently corrupted the stack. When a Watchdog timeout occurs, the MAX1780 microcontroller core is reset and the entire boot-up process is repeated. Figure 12 shows the Watchdog Timer and how i is derived from Timer B. Timer B is a free running 16-bit ripple counter, and is t clocked by the 32KHz oscillator. Timer B reaches its maximum count each second, and will overflow, setting the flip-flop connected to its output. If the flip-flop is not cle ared, by executing a CLRWDT instruction, by the time Timer B overflows again (2 seconds), the second flip-flop toggles, resulting in a reset of the MAX1780. The Watchdog timeout is held off or cleared by executing a CLRWDT instruction before the Watchdog's timer period has expired. Good programming practice will insure that CLRWDT instructions are properly distributed to prevent a Watchdog timeout in normal operation. A word of caution, executing the SLEEP or OPTION instructions does NOT clear the watchdog timeout.
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Advanced Smart Battery Pack Controller
Interrupts
Description
The MAX1780 CPU interrupt structure is depicted in Figure 13 below. All interrupts vector program execution to memory address 0x0200. All interrupts have the same priority. The first interrupt input (INT1) is connected to pin IO7, and may be used by external circuitry. The second interrupt input (INT2), is used exclusively by the SMBus Interface. Within the SMBus Interface, there are multiple interrupt sources. Please refer to the SMBus section of this document for details. The third interrupt input (INT3), is driven by the Peripheral Interrupt Controller. This block has mask and status registers for eight peripheral interrupt sources. Please refer to the Peripheral interrupt Controller section for details.
OVFL TIMER A & B
INT1
IO7 PIN
INT2
SMBus Interface
MAX1780 PROCESSOR CORE
POWER FAIL FG DIRECTION ADC DONE
INT3
Peripheral Interrupt Controller
DETECT PIN OVERCHARGE OVERDISCHARGE FG CHG OVERFLOW FG DIS OVERFLOW
Figure 13, MAX1780 Interrupt Structure
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Advanced Smart Battery Pack Controller
Peripheral Interrupt Control Registers
The Peripheral Interrupt Control registers INTSTAT and INTREN funnel all of the on board peripheral interrupt sources to INT3 in the MAX1780 core. The only exceptions are the interrupts generated by the SMBus Interface, which are routed to INT2. The INTSTAT Register latches the interrupt events so that they can provide status, which can be read at any time. The INTREN Register is provided to enable or disable interrupts to INT3. Please note that even though a particular interrupt can be disabled (masked) by clearing the appropriate bit in the INTREN Register, the associated interrupt flag in the INTSTAT Register will still be set when the interrupt occurs. Figure 14 shows the INSTAT and INTREN registers, and how they interact to provide interrupt control and status.
L A T C H
CLR PORTB PERIPHERAL BUS
PFW FGDIR ADCDONE DETECT OCINT ODINT FGCHGOVFL FGDISOVFL
D7 D6 D5 D4 D3 D2 D1 D0 8 INTSTAT REGISTER Write '1' to Status bit to Clear the Interrupt
D7 D6 D5 D4 D3 D2 D1 D0 8 INTREN REGISTER
OR
INT3
Figure 14, Peripheral Interrupt Control Registers
Interrupt Status Register (INTSTAT) Operation
The Interrupt Status Register latches interrupt events from 8 peripheral sources. When a peripheral interrupt occurs, the corresponding bit in the INTRSTAT Register will be set. It can be read through the PORTB Interface any number of times without affecting the state of the status flags. This is true regardless of the interrupt enable register settings. Writing a `1' to a particular bit in the interrupt status register will clear the interrupt status corresponding to that bit.
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Advanced Smart Battery Pack Controller
Interrupt Enable Register (INTREN) Operation
The Interrupt Enable Register (INTREN) controls which peripheral interrupt sources will trigger Interrupt 3 (INT3) in the MAX1780 CPU. The register values can be read through the PORTB Interface any number of times without affecting their state. The Interrupt Enable Register bits will be cleared to `0' whenever MCLR is asserted low or a power on reset (POR) occurs. Clearing the bits in this register does not prevent the INTSTAT Register from latching peripheral interrupts that occur, this only masks them from INT3.
Interrupt Control Register Descriptions
INTSTAT Register (Read/Write):
Bit D7 Name PFW POR 0
PORTB Address = 0x0E
Function/Description Power Fail Warning. VAA Supply > 3V After POR, Or Has Fallen Below 3V During Operation. D6 FGDIR 0 Fuel Gauge Direction Change. D5 ADC 0 ADC conversion start and completion. D4 DETECT 0 A Rising Or Falling Edge On The DETECT Pin Has Occurred. D3 OCINT 0 Charge Current Limit Exceeded. D2 ODINT 0 Discharge Current Limit Exceeded. D1 FGCHGOVFL 0 Fuel Gauge Charge Counter Overflow. D0 FGDISOVFL 0 Fuel Gauge Discharge Counter Overflow. Note: The register is read to determine the interrupt status. To clear an interrupt, write a `1' to the bit that corresponds to the interrupt.
INTREN Register (Read/Write):
Bit D7 D6 D5 D4 D3 D2 D1 D0 Name PFWMSK FGDIRMSK ADCMSK DETMSK OCIMSK ODIMSK FGCHGMSK FGDISMSK POR 0 0 0 0 0 0 0 0 Function/Description 0 - PFW Interrupt Masked. 1 - PFW Interrupt Enabled. 0 - FGDIR Interrupt Masked. 1 - FGDIR Interrupt Enabled. 0 - ADC Interrupt Masked. 1 - ADC Interrupt Enabled. 0 - DETECT Interrupt Masked. 1 - DETECT Interrupt Enabled. 0 - OCINT Interrupt Masked. 1 - OCINT Interrupt Enabled. 0 - ODINT Interrupt Masked. 1 - ODINT Interrupt Enabled. 0 - FGCHGOVFL Interrupt Masked. 1 - FGCHGOVFL Interrupt Enabled. 0 - FGDISOVFL Interrupt Masked. 1 - FGDISOVFL Interrupt Enabled.
PORTB Address = 0x0F
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Advanced Smart Battery Pack Controller
Analog Peripherals
3.5MHz Instruction Oscillator
The MAX1780 contains an internal instruction execution oscillator that does not require an external crystal for operation. It is factory trimmed to 3.5MHz. In sleep mode the internal instruction oscillator can be turned off to save power. The internal oscillator is guaranteed to start up within 2 s, minimizing interrupt latency. Any interrupt automatically exits sleep mode. The OSLB bit in the OPTION register controls whether or not the internal instruction oscillator is turned off in sleep mode. The internal instruction oscillator turns on whenever sleep mode is exited regardless of the condition of the OSLB bit.
32KHz Oscillator
The 32KHz oscillator is used by several of the MAX1780 peripherals. It provides input clocks for TIMERA, TIMERB, the Data Acquisition Unit, and the Fuel Gauge. The oscillator requires only an external 32.768KHz watch crystal for proper operation. The 32KHz Oscillator is a Pierce-type crystal oscillator in which the output frequency is tuned by varying the total capacitance across the crystal's terminals. This capacitance is referred to as the "Load Capacitance" CL on crystal datasheets, and can vary depending on the manufacturer. Load Capacitance is calculated as follows: CL = C OSC + CPCB + C0 Where C y OSC is the MAX1780's on-chip load capacitance (2.5pF t pical), CPCB is PCB layout parasitic capacitance, and C0 is the shunt capacitance of the 32KHz watch crystal. For reliable oscillator start-up under worst-case conditions, insure that CL is less than 7pF. We do not recommend adding external capacitance to tune the oscillator frequency. Use caution when connecting an oscilloscope probe to OSC1, the 10pF scope probe capacitance is large enough to stop the 32KHz oscillator.
Low Drop Out Linear Regulator
The Low Drop Out Linear Regulator Unit regulates a 4V to 28V DC input voltage on the BATT pin, down to 3.4V. The 3.4V supplies the MAX1780 internal circuitry, and is available for external circuitry on the VAA output pin. Please note that for proper operation, the VAA and VDD pins must be connected as close as possible to the chip. The VAA output can supply 3.4V to external loads at up to 10mA. The Linear Regulator's current limit is typically 40mA. The VAA output should be bypassed with a 0.47F capacitor to ground.
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Advanced Smart Battery Pack Controller
Precision Bandgap Reference
The Precision Bandgap Reference provides 1.217V to the Data Acquisition Block. It is used internally and not brought out to a pin. The MAX1780 powers up with this reference shutdown and before attempting to make any measurements with the Data Acquisition Unit or Fuel Gauge, the user must write a `1' to bit D7 of the REFCONFIG Register.
REFCONFIG Register (Write Only):
Bit D7 D6 D5 D4 D3 D2 D2 D2 Name REFON RFU RFU RFU RFU RFU RFU RFU POR 0 Function/Description 0 = Reference OFF 1 = Reference ON Data bit 6 Data bit 5 Data bit 4 Data bit 3 Data bit 2 Data bit 1 Data bit 0
PORTB Address = 0x09
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Advanced Smart Battery Pack Controller Mixed Signal Peripherals
Fuel Gauge Unit
General Description
The Fuel Gauge measures the cumulative charge into (charging) and out of (discharging) the system battery pack and stores the information in one of two internal, independent charge and discharge counters. The unit also informs the host of changes in the direction of current flow. Communication with the Fuel Gauge is via Port B, and allows access to charge/discharge counters and internal registers.
Features
* * * * * True Coulomb Counting, Integrating Fuel Gauge Separate 16-bit Charge and Discharge Counters Counter Overflow and Current Direction Change Interrupts 4 Counter Latching Sources Automatic Cancellation Of Input Offset Voltage
8
FGCONFIG2
8
Reference Logic Control
Interrupt
8
FGCONFIG1
8
DIS Latch Command ADC Start/Stop Timer A Overflow Timer B Overflow CHG
Interleaved Bidirectional Charge Pump
2.0 V
Synch
CP A CPB
Peripheral Data Bus (8-bits)
Charge Count (16-bits)
COMP 2.0 V B4
8
8
FGCHGHIGH
REF/2 8
8
B3
FGCHGLOW
CINT
B2
B1 1.0 V RINT CS+ AMP Chopper Stabilized 8 8
Discharge Count (16-bits)
COMP
IBATT
CS-
Analog Section
8
FGDISHIGH
8
FGDISLOW
Figure 15, Fuel Gauge Block Diagram
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Advanced Smart Battery Pack Controller
Automatic Cancellation Of Input Offset Voltage
The MAX1780 Fuel Gauge uses a Chopper-Stabilized amplifier to couple the voltage across the current sense resistor to the Voltage-To-Frequency converter. This voltage, which can be a high as +/- 137.33mV at heavy load currents, can be only a few microvolts at light loads. Therefore, the amount of input offset voltage determines the minimum current sensitivity of the fuel gauge. The Chopper-Stabilized amplifier continually samples and corrects for its inherent offset. This cancellation occurs in conjunction with the Fuel Gauge's Coulomb counting circuitry. While the circuit is performing Fuel Gauge measurements, it is continually canceling the internal input offset voltage. The MAX1780 Fuel Gauge therefore, requires no software calibration. With careful attention to PCB layout, input offsets of less than 1V can be expected.
Coulomb Counting
The Fuel Gauge's Coulomb counting circuit monitors the differential voltage present at the CS+ and CS- pins. In a typical application, the CS+ and CS- pins are connected across a sense resistor that is in series with the battery pack cells. This voltage is converted to a frequency proportional to the rate at which the current is flowing through the sense resistor, and the circuit counts Coulombs of charge by incrementing either the Charge Counter or the Discharge Counter accordingly.
Charge And Discharge Counters
Figure 15 shows the functional diagram of the Fuel Gauge's Coulomb-counter section. The Coulomb counter's output increments (but never decrements) one of two independent 16-bit counters: Charge Count for charging currents, and Discharge Count for discharging currents. By independently counting the charge and discharge currents, the Fuel Gauge can accommodate any algorithm to account for battery pack energy-conversion efficiency. The 16-bit Charge and Discharge Count latch registers are each div ided into 2 bytes: FGCHGLOW, FGCHGHIGH, FGDISLOW, and FGDISHIGH. See the Fuel Gauge Register Descriptions for details of the different registers. Charge Count and Discharge Count reset to zero whenever a power-on reset executes, or when the configuration word's FGCLRCHG FGCLRDIS bits are set. Use of the FGCLRCHG and FGCLRDIS bits to clear the fuel gauge counters is not recommended as part of a fuel gauging algorithm, as it is possible to loose counts during the clear operation. Each counter also resets any time an overflow condition occurs. When a counter overflows, it simply clears and begins counting from 0. Interrupts are generated on counter overflows unless they are masked by the FGCHGOVFL and FGDISOVFL bits in the Interrupt Controller INTREN register. Writing a one to the FGLATCHNOW bit in the Fuel Gauge's FGCONFIG2 Register latches the instantaneous counts for both the Charge and Discharge Counters without clearing the counters. The 16-bit charge count value can be obtained by reading the data in the FGCHLOW and FGCHGHIGH latch registers. Similarly, the Discharge Count can be obtained by reading the data in the FGDISLOW and FGDISHIGH registers. The gain factor is the constant of proportionality that relates the counter values stored in the Charge Count and Discharge Count registers to the amount of charge flow into or out of the battery pack. The electrical characteristics table specifies the maximum v-to-f converter frequency and the full-scale sense resistor voltage. With these two values the gain factor (FGGAIN) can be calculated as follows:
Determining Fuel Gauge Gain:
FG GAIN = 50 KHz 137.33 mV FGGAIN = 3.641 x 10
5
Hz V
Multiplying the sense resistor value by the Gain Factor, the number of counter increments generated per Coulomb can be determined.
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Advanced Smart Battery Pack Controller
Determining Fuel Gauge Count Rate:
Given: Count RCS = 0.020
RATE
= RCS FGGAIN Count
RATE
= 7.282 x 10
3
Count C
Therefore, a 20m current-sense resistor sets up a counter rate of 7.28 x 103 counts per Coulomb. A higher conversion gain (larger RCS) increases resolution at low currents, but limits the maximum measurable current. Likewise, a smaller conversion gain (smaller R ) decreases resolution at low c urrents, but increases the CS maximum measurable current. This provides a good balance between resolution and input current range for many applications.
Calculating The Fuel Gauge "Bucket" Size:
Given: RCS = 0.020 1 Count
RATE
FGBUCKET_SIZE =
1000 mA 65536 Count 3600 sec 1 A 1 Overflow
1 hr
FGBUCKET_SIZE = 2.5
mA hr Overflow
The fuel gauge "bucket" size, which is the amount of energy necessary to overflow either the charge or discharge counters, is an integral factor in calculating a battery's remaining capacity. Knowing the amount of charge or discharge energy at each overflow interrupt, in milliamp-hours, makes updating the calculated battery remaining capacity as simple as adding and subtracting. In the example above, with RCS equal to 0.020, the fuel gauge charge or discharge counters will trigger an interrupt whenever 2.5 mAh of energy has flowed into or out of the battery.
Current Direction Change Detection Function
The Fuel Gauge's direction-change detection function informs the host whenever the current flow changes direction. The direction-change function is simple: the FGCONFIG1 Register FGCHGSTAT bit is set to 1 when the voltage potential across CS+ and CS- is positive. When the voltage from CS+ to CS- is negative (discharge) this status bit is set to 0. The FGCHGSTAT bit is READ ONLY. The INTSTAT Register, in the peripheral interrupt controller, has a dual edge triggered input for the FGCHGSTAT bit called FGDIR. FGDIR sets anytime there is a change in current flow direction on the sense resistor. This is useful for interrupting the CPU for routines in which the host must be informed immediately of a change in current-flow direction. To enable this interrupt set the FGDIR bit in the INTREN Register to a `1' (See the section on Peripheral Interrupt Controller).
Counter Latching Source And Arbiter
The FGMUX bits in the FGCONFIG1 Register select one of four sources for latching the Fuel Gauge's charge and discharge counter values.
Direct CPU Control
The fuel gauge charge and discharge counter values can be latched under direct CPU control by first setting the FGMUX bits D4 and D5 to `00' in the FGCONFIG1 Register, and then writing a `1' to the FGLATCHNOW bit D7 in the FGCONFIG2 Register. This action essentially takes a "snapshot" of the instantaneous counter values
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Advanced Smart Battery Pack Controller
and stores them in the FGDISHIGH, FGDISLOW, FGCHGHIGH, and FGCHGLOW Registers. The charge and discharge counters are not affected by the latching operation.
ADC Conversion Start and Stop
Setting the FGMUX bits D4 and D5 to `01' will cause the Fuel Gauge charge and discharge counter values to be latched at the beginning and end of each ADC conversion. This method of latching the Fuel Gauge counters allows the simultaneous measurement of cell voltage and current, which can be used to determine instantaneous cell impedance.
TIMERA Overflow
The Fuel Gauge charge and discharge counter values can be latched by each TIMERA overflow by setting the FGMUX bits D4 and D5 to `10'. TIMERA is a 16-bit programmable counter that can be clocked by several sources. This method for latching the Fuel Gauge counters is for determining the accumulated charge/discharge for an arbitrary time interval.
TIMERB Overflow
The Fuel Gauge charge and discharge counter values can be latched by each TIMERB overflow by setting the FGMUX bits D4 and D5 to `11'. TIMERB is clocked by the 32KHz Oscillator and is generally programmed to overflow at 1sec intervals. This latching method can then be used to capture charge and discharge counter values accumulated between the 1sec overflows. The difference between two successive counter values is the amount of charge that flows in 1sec, which is also the instantaneous current that is flowing.
Arbitration Logic
The charge and discharge counters increment asynchronous with respect to the MAX1780 CPU instruction execution. Also, each of the four counter latching sources can occur asynchronously with respect to charge and discharge counter updates. To insure that erroneous counter values are not latched, the Fuel Gauge employs specia l arbitration logic. There is no arbitration while switching modes; therefore it is prudent to only trust data that has been latched by the most recently selected mode.
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Advanced Smart Battery Pack Controller
Fuel Gauge Register Descriptions
FGCONFIG1 (Read/Write)
Bit D7 D6 D5 D4 Name FGON FGCALON FGMUX[1:0] POR 0 0 00
PORTB Address = 0x18
Function/Description Writing a "1" turns ON the Fuel Gauge Block 0 = Track the charge flow between CS+ and CS1 = Internally connects CS+ to CS-. Note the CS+ pin is high impedance. FGMUX[1:0] chooses the source signal for latching counter data. 00 = Enables functions in FGCONFIG2 01 = Charge and discharge counts are latched at the start and completion of an ADC conversion. 10 = Charge and discharge counts are latched by each TIMERA overflow. 11 = Charge and discharge counts are latched by each TIMERB overflow. 0 = Discharge current direction. 1 = Charge current direction. (This bit is READ ONLY) Read Only Read Only Read Only
D3
FGCHGSTAT
-
D2 D1 D0
RFU RFU RFU
0 0 0
FGCONFIG2 (Write Only)
Bit D7 Name
FGLATCHNOW
PORTB Address = 0x19
Function/Description * Writing a "1" into this bit latches the contents of the Fuel Gauge counters into FGDISHIGH, FGDISLOW, FGCHGHIGH, and FGCHGLOW. * Writing a `1' into this bit clears the discharge counter * Writing a `1' into this bit clears the charge counter
POR -
D6 D5 D4 D3 D2 D1 D0
FGCLRDIS FGCLRCHG RFU RFU RFU RFU RFU
-
* Note: This Register is only operational when FGMUX[1:0] = 00
FGDISLOW Register (Read Only):
Bit D7 D6 D5 D4 D3 D2 D1 D0 Name FGD_D7 FGD_D6 FGD_D5 FGD_D4 FGD_D3 FGD_D2 FGD_D1 FGD_D0 POR 0 0 0 0 0 0 0 0 Function/Description Fuel Gauge discharge count latch Bit 7 Fuel Gauge discharge count latch Bit 6 Fuel Gauge discharge count latch Bit 5 Fuel Gauge discharge count latch Bit 4 Fuel Gauge discharge count latch Bit 3 Fuel Gauge discharge count latch Bit 2 Fuel Gauge discharge count latch Bit 1 Fuel Gauge discharge count latch Bit 0
PORTB Address = 0x1A
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Advanced Smart Battery Pack Controller
FGDISHIGH Register (Read Only):
Bit D7 D6 D5 D4 D3 D2 D1 D0 Name FGD_D15 FGD_D14 FGD_D13 FGD_D12 FGD_D11 FGD_D10 FGD_D9 FGD_D8 POR 0 0 0 0 0 0 0 0 Function/Description Fuel Gauge discharge count latch Bit 15 Fuel Gauge discharge count latch Bit 14 Fuel Gauge discharge count latch Bit 13 Fuel Gauge discharge count latch Bit 12 Fuel Gauge discharge count latch Bit 11 Fuel Gauge discharge count latch Bit 10 Fuel Gauge discharge count latch Bit 9 Fuel Gauge discharge count latch Bit 8
PORTB Address = 0x1B
FGCHGLOW Register (Read Only):
Bit D7 D6 D5 D4 D3 D2 D1 D0 Name FCD_D7 FCD_D6 FCD_D5 FCD_D4 FCD_D3 FCD_D2 FCD_D1 FCD_D0 POR 0 0 0 0 0 0 0 0 Function/Description Fuel Gauge charge count latch Bit 7 Fuel Gauge charge count latch Bit 6 Fuel Gauge charge count latch Bit 5 Fuel Gauge charge count latch Bit 4 Fuel Gauge charge count latch Bit 3 Fuel Gauge charge count latch Bit 2 Fuel Gauge charge count latch Bit 1 Fuel Gauge charge count latch Bit 0
PORTB Address = 0x1C
FGCHGHIGH Register (Read Only):
Bit D7 D6 D5 D4 D3 D2 D1 D0 Name FGC_D15 FGC_D14 FGC_D13 FGC_D12 FGC_D11 FGC_D10 FGC_D9 FGC_D8 POR 0 0 0 0 0 0 0 0 Function/Description Fuel Gauge charge count latch Bit 15 Fuel Gauge charge count latch Bit 14 Fuel Gauge charge count latch Bit 13 Fuel Gauge charge count latch Bit 12 Fuel Gauge charge count latch Bit 11 Fuel Gauge charge count latch Bit 10 Fuel Gauge charge count latch Bit 9 Fuel Gauge charge count latch Bit 8
PORTB Address = 0x1D
42
Advanced Smart Battery Pack Controller Data Acquisition Unit
General Description
The MAX1780 Data Acquisition Unit combines a high voltage Analog Front End/Multiplexer (AFE), and precision integrating Analog To Digital Converter (ADC). The AFE can be directly connected with up to four series lithium ion cells, and can be configured to provide eighteen different voltage measurements. The AnalogTo-Digital Converter can be configured to make conversions at four resolutions: 11, 13, 15, and 16 bits, and will automatically shutdown after conversions to conserve power. Communication to and from the Data Acquisition Unit is via the PORTB peripheral interface. Figure 16 below shows the architecture of the unit.
Features
* * * * * * * * Differential Measurement Of Individual Cell Voltages Automatic Cancellation Of AFE Input Bias Currents User Selectable ADC Resolutions (11, 13, 15 and 16 bits) Automatic Shutdown Upon Conversion Completion Conversions Independent Of CPU Operation User maskable Interrupt upon end of conversion On-chip Temperature Sensor Maximum Differential Cell Voltage Measurement Error +/-50mV
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Advanced Smart Battery Pack Controller
8
AFECONFIG
8
ADCCONFIG
FINISH START
Reference
Interrupt
REVERSE
Control Logic + Resolution Counter 18-bit Up/Down Counter
Peripheral Data Bus (8-bits)
SIGN OVERFLOW
8
BP4 REF
PVFUP
C INT
PV
Window Comparator
PVFDN
BP3
CP A REF Charge Pump CP B C INT
BP2 AGND BP1
CONVERSION DONE
18
REF
18-bit Up/Down Counter
18
NV
NVFUP
AFE + MUX
BN
Window Comparator
NVFDN
CP A AGND REF Charge Pump CP B AGND
18-bit Adder
ADC Analog Section
8
AIN
8
ADCHIGH
8
VDD VREF
8
ADCLOW
Internal Temperature Sensor
TEMP
Figure 16, Data Acquisition Unit Block Diagram
Analog Front End/Multiplexer (AFE)
The Analog Front End selects and scales the desired input signal for the ADC. The AFE allows the user to make four types of precision measurements selectable through the AFEMODE bits in the AFECONFIG Register: Voltage Range 0 to 5.12V 0 to 20.48V 0 to 20.48V 0 to 20.48V Connection Type Single-ended referred to AGND Single-ended referred to BN Single-ended referred to AGND Differential
The AFESELECT bits in the AFECONFIG register allow the user to choose a particular signal within each Mode. This equates to a total of 14 Single -ended and 4 Differential measurements.
Input Bias Cancellation
While the MAX1780's ADC measures battery pack cell voltages, each connection to the ADC connects a 4 MegOhm resistor from the measured pin to ground during conversion. Although the resulting input bias current
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Advanced Smart Battery Pack Controller
is small, even small currents from intermediate cell stack voltages can imbalance a cell stack over time. To protect against this, the MAX1780 incorporates a special input bias current cancellation circuit (ICAN). Programming the number of series cells in the AFECONFIG register automatically enables the ICAN circuit for an intermediate cell voltage measurement during a conversion. Note that while the ICAN circuit is enabled, about 65uA of additional supply current is drawn from the B4P pin for each pin whose input bias current is being cancelled. When enabled, the ICAN circuit will typically reduce the uncanceled input bias current by a factor of 100.
AFE Register Descriptions
AFECONFIG (Read/Write)
Bit D7 D6D5 Name CELLCNT POR 0 0
PORTB Address 0x10
Function/Description Unused R/W bit. Selection of battery pack cell count: (Used only for input bias current cancellation) 00 = Input Bias Current Cancellation Off. 01 = 2 Cells. Input bias current canceled for B1P only. 10 = 3 Cells. Input bias current canceled for B1P and B2P. 11 = 4 Cells. Input bias current canceled for B1P, B2P, and B3P. Note: Refer to Figure 27 for the proper connections for 2, 3, and 4 series cell configurations. Selection of ADC measurement Mode: 00 = Configures AFE for low-voltage measurements, referred to AGND 01 = Configures AFE for high-voltage measurements, referred to BN 10 = Configures AFE for high-voltage measurements, referred to AGND 11 = Configures AFE for high-voltage differential measurements Selection of analog signal to measure: AFEMODE = 00 (Low-voltage, Range: 0 to 5.12V): 000 = AGND, Referred to AGND 001 = Internal Temperature Measurement, Referred to AGND 010 = VDD, Referred to AGND 011 = VREF, Referred to AGND 100 = BN, Referred to AGND 101 = AIN, Referred to AGND 11x = undefined AFEMODE = 01 (High-voltage, Range: 0 to 20.48V): 000 = B1P, Referred to BN 001 = B2P, Referred to BN 010 = B3P, Referred to BN 011 = B4P, Referred to BN 1xx = undefined AFEMODE = 10 (High-voltage, Range: 0 to 20.48V): 000 = B1P, Referred to AGND 001 = B2P, Referred to AGND 010 = B3P, Referred to AGND 011 = B4P, Referred to AGND 1xx = undefined
45
D4D3
AFEMODE
00
D2D0
AFESELECT
000
Advanced Smart Battery Pack Controller
AFEMODE = 11 (High-voltage differential, Range: 0 to 20.48V): 000 = B1P - BN 001 = B2P - B1P 010 = B3P - B2P 011 = B4P - B3P 1xx = undefined
Analog-To-Digital Converter (ADC)
Operation
To perform an ADC conversion, first program the AFECONFIG Register with the number of series cells, and then select the desired measurement mode. Start the conversion by setting the ADCSTCONV bit to a "1" in the ADCCONFIG register. This will cause the peripheral to power-up and begin a conversion. Upon completion of the conversion, the control logic clears the ADCSTCONV bit in the ADCCONFIG register. The conversion result can be read from the ADCHIGH and ADCLOW Registers. If the ADCINTON bit in the ADCCONFIG register is set to "1", an interrupt will occur at the beginning and end of each ADC conversion. At the end of each conversion cycle the ADC will automatically power itself down to conserve energy.
Dual Voltage-To-Frequency Converter
Each V-to-F Converter changes an applied input voltage to a proportional output frequency. This frequency is in-turn sent to a window comparator that determines if an LSB of change with respect to the reference has occurred. PVFUP and NVFUP pulses are generated for each LSB change in the positive direction, and correspondingly PVFDN and NVFDN pulses are generated for each LSB change in the negative direction. Each V-to-F converter has a charge pump which restores current to the summing node of the converter.
Digital Counter/Adder
There are two 18-bit up/down counters whose counts are 1's complement added to obtain a 16-bit binary conversion value. Although the highest resolution conversion is 16 bits, the counters and adder are 18 bits wide to implement sign and overflow. The final ADC result is formed by an 18-bit adder, which sums the two counter outputs. The MAX1780 CPU can read the conversion results as two bytes.
Control Logic And Resolution Counter Block
The Control Logic And Resolution Counter Block is clocked by the 32KHz oscillator, and interprets the ADCCONFIG Register bits. It controls the state timing of a conversion cycle and as well as determining the conversion resolution.
Over-Range Status And Limit Bits
The MAX1780 Data Acquisition Unit has special circuitry to handle and report status on conversions where the measured input voltage is outside of the ADC's full-scale voltage ranges of 5.12V or 20.48V. The SIGN and OVERFLOW bits provide over-range status information, and the LIMIT bit restricts ADC conversion results.
The OVERFLOW Bit
Whenever an ADC conversion is attempted on a positive or negative voltage outside the selected range, the OVERFLOW bit, D7 in the ADCCONFIG Register, will be set.
The SIGN Bit
The SIGN Bit, D6 in ADCCONFIG Register, will be set whenever an ADC conversion results in a negative value.
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Advanced Smart Battery Pack Controller
The LIMIT Bit
The Limiting function, when enabled, will limit positive over-range conversion results to 0xFFFF, and negative over-range values to 0x0000. When Limiting is disabled, over-range conversion results will roll over. To enable the Limiting function, set bit D5 in the ADCCONFIG Register to `1'.
Understanding ADC Error Sources
This ADC has four sources of error: Gain Error: The ADC gain error is influenced by trimming resolution, temperature coefficient of the precision reference and v-to-f converters, gain matching between the various input channels of the ADC, and accuracy of the 32768Hz crystal time base. Note that it may take up to 4 seconds for the 32KHz oscillator to stabilize after power up. The ADC is trimmed to be most accurate at the B4P to B1P inputs. This error will total to about 0.5%. Offset Error: The input offset of the two v-to-f converters will introduce an offset error into the result. The typical offset error is around 100uV and becomes negligible in most conversions. Common-Mode Error: This source of error only comes into play for high-voltage differential measurements. Matching between the positive and negative input channels of the measurement will introduce an error proportional to the common-mode voltage. What this means is if B4P=B3P=20V, the converter may measure 10mV; when B4P=B3P=10V, this same converter would measure 5mV. Quantization Error: Each v-to-f converter has +/-0.5 bits of quantization error. When the results of the two vto-f converters are digitally subtracted, this becomes +/-1 bits of quantization error. Because each full conversion actually consists of two consecutive conversions with the v-to-f converters swapped, the total quantization error becomes +/-2 bits. Note that although it is theoretically possible to see 2 bits of quantization error, it is unlikely, and most conversions will show +/-0.5 bits of quantization error. Still, for the various resolutions, the worse case quantization error becomes:
Resolution 11 bits 13 bits 15 bits 16 bits
Effective Resolution 9 bits 11 bits 13 bits 14 bits
HV quantization error 40mV 10mV 2.5mV 1.25mV
LV quantization error 10mV 2.5mV 0.625mV 0.3125mV
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Advanced Smart Battery Pack Controller
Effective ADC Resolution
As explained in the "Understanding ADC Error Sources" section, each ADC conversion cycle averages the results of two sub-conversions with the V-to-F converters swapped. The digital subtraction in conjunction with the V-to-F converter swapping creates +/-2 LSB's of quantization error. Therefore, the effective ADC resolutions are as shown in Figure 17 below.
ADCHIGH
D15 D14 B14 D13 B13 D12 B12 D11 B11 D10 B10 D9 B9 D8 B8 D7 B7 D6 B6 D5 B5
ADCLOW
D4 B4 D3 B3 D2 B2 D1 B1 D0 B0
ADCRES = 0b11 (16-Bits)
B15
EFFECTIVE RESOLUTION = 14 Bits
QUANTIZATION ERROR
ADCHIGH
D15 D14 B13 D13 B12 D12 B11 D11 B10 D10 B9 D9 B8 D8 B7 D7 B6 D6 B5 D5 B4
ADCLOW
D4 B3 D3 B2 D2 B1 D1 B0 D0 0
ADCRES = 0b10 (15-Bits)
B14
EFFECTIVE RESOLUTION = 13 Bits
QUANTIZATION ERROR
ADCHIGH
D15 D14 B11 D13 B10 D12 B9 D11 B8 D10 B7 D9 B6 D8 B5 D7 B4 D6 B3 D5 B2
ADCLOW
D4 B1 D3 B0 D2 0 D1 0 D0 0
ADCRES = 0b01 (13-Bits)
B12
EFFECTIVE RESOLUTION = 11 Bits
QUANTIZATION ERROR
ADCHIGH
D15 D14 B9 D13 B8 D12 B7 D11 B6 D10 B5 D9 B4 D8 B3 D7 B2 D6 B1 D5 B0
ADCLOW
D4 0 D3 0 D2 0 D1 0 D0 0
ADCRES = 0b00 (11-Bits)
B10
EFFECTIVE RESOLUTION = 9 Bits
QUANTIZATION ERROR
Figure 17, Effective ADC Resolutions
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Advanced Smart Battery Pack Controller
ADC Register Descriptions
ADCCONFIG (Read/Write)
Bit D7 D6 D5 Name OVERFLOW SIGN ADCLIMIT POR 0 0 1
PORTB Address = 0x11
Function/Description 0 = In Range 1 = Overflow 0 = Positive overflow 1 = Negative overflow 1=Limiting On. 0=Limiting Off. Limiting only affects what is read from ADC_LO/ADC_HI = {0x12 and 0x13}. Conversion does not have to be repeated to toggle between limited and non-limited results. 1 = Offset cancellation enabled. (Always leave on for best performance) 0 = Offset cancellation disabled. 1= Enables ADC interrupts. Interrupts occur at the beginning and end of a conversion cycles. 00: Resolution 11 bits. (9 bits effective with +/-2 bits of quantization error) 01: Resolution 13 bits. (11 bits effective with +/-2 bits of quantization error) 10: Resolution 15 bits. (13 bits effective with +/-2 bits of quantization error) 11: Resolution 16 bits. (14 bits effective with +/-2 bits of quantization error) Writing a "1" to this bit starts a conversion cycle. Upon completion of a conversion cycle, the ADC logic will reset this bit to "0" indicating that sampled data is ready to be read.
D4 D3 D2 D1
CHOPON ADCINTON ADCRES[1:0]
1 0 01
D0
ADCSTCONV
0
ADCLOW (Read Only)
Bit D7 D6 D5 D4 D3 D2 D1 D0 Name ADC_D7 ADC_D6 ADC_D5 ADC_D4 ADC_D3 ADC_D2 ADC_D1 ADC_D0 POR 0 0 0 0 0 0 0 0 Function/Description ADC Sample Bit 7. ADC Sample Bit 6 ADC Sample Bit 5. (11 Bit LSB) ADC Sample Bit 4. ADC Sample Bit 3. (13 Bit LSB) ADC Sample Bit 2. ADC Sample Bit 1. (15 Bit LSB) ADC Sample Bit 0. (16 Bit LSB)
PORTB Address = 0x12
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Advanced Smart Battery Pack Controller
ADCHIGH (Read Only)
Bit D7 D6 D5 D4 D3 D2 D1 D0 Name ADC_D15 ADC_D14 ADC_D13 ADC_D12 ADC_D11 ADC_D10 ADC_D9 ADC_D8 POR 0 0 0 0 0 0 0 0
PORTB Address = 0x13
Function/Description ADC Sample Bit 15. (11/13/15/16 Bit MSB) ADC Sample Bit 14. ADC Sample Bit 13. ADC Sample Bit 12. ADC Sample Bit 11. ADC Sample Bit 10. ADC Sample Bit 9. ADC Sample Bit 8.
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Advanced Smart Battery Pack Controller
Temperature Sensor
Description
The MAX1780 has an on-chip temperature sensor, a bi-polar Proportional To-Absolute-Temperature (PTAT) transistor, which closely tracks the MAX1780 die temperature. The temperature measurement results are in degrees Kelvin.
Operation
To make a temperature measurement, use the following procedure: 1. Set the AFECONFIG Register AFEMODE[4:3] bits to `00'. 2. Set the AFECONFIG Register AFESELECT[2:0] bits to `001' to select the on-chip temperature sensor. 3. Write a `1' to the ADCCONFIG Register ADCSTCONV bit to trigger an ADC conversion. 4. Read the measurement results from the ADCHIGH and ADCLOW Registers. Figure 18 below depicts the individual bit weights, in degrees Kelvin , for temperature measurement conversion values at 16 bits of resolution. An 11-bit conversion will have a worse case quantization error of +/- 1K. To convert the temperature in degrees Kelvin to degrees Celsius, subtract 0x8893 from the measured result.
ADCHIGH
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5
ADCLOW
D4 D3 D2 D1 D0
0.0078125 K 0.015625 K 0.03125 K 0.0625 K 0.125 K 0.25 K 0.5 K 1 K 2 K 4 K 8 K 16 K 32 K 64 K 128 K 256 K
QUANTIZATION ERROR
EFFECTIVE RESOLUTION = 14 Bits
Figure 18, Temperature Conversion Bit Weights
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Advanced Smart Battery Pack Controller
Overcurrent Protection Block
Description
The MAX1780's Overcurrent Protection Block continuously monitors the current flowing through the battery pack sense resistor and compares this with the user adjustable thresholds for Overcharge and Overdischarge current. The Overcurrent Protection block will continue to provide protection even when the MAX1780 processor core is shutdown (SLEEP). Figure 19 below shows the functional diagram of the over-current comparator section. An overcurrent condition occurs whenever the voltage on CS+ exceeds the voltage on OCI (for charging currents), or when ODI falls below CS- (for discharging currents). When an over-current condition occurs, the overcurrent comparators generate an interrupt to the processor core, as well as set the OD (discharging) or OC (charging) latch. These latches remain set until a `1' is written to the appropriate bit (D2 or D3) of the INTRSTAT Register, or the MAX1780 initiates a power-on reset. A logic block follows the latch, which sets the gate -driver output's appropriate state, as defined in Table 1 and Table 2, and drives the N-channel MOSFET open-drain gate drivers.
0.3V
BATT Q DIS Q
CLR
DETECT D
VDD CMPDISSYSPOL
DISCHARGE LOGIC
CMPDISSYSEN CMPDISHI
OD INT ODINT
COMP
ODI
Q
SET
S
+
Note: MCLR\ = 0 forces CHG and DIS to be high impedance and resets both ODINT and OCINT.
CS-
Q CLR R
ODINTCLR
0.3V
The ODINTCLR signal is generated by writing a '1' to bit D2 of the INTRSTAT Register.
Q CHG Q
CLR
D
VDD
CMPCHGSYSPOL
CHARGE LOGIC
CMPCHGSYSEN CMPCHGHI
OC INT OCINT
COMP
OCI
Q
SET
S
+
Q CLR R
The OCINTCLR signal is generated by writing a '1' to bit D3 of the INTRSTAT Register. OCINTCLR
CS+
Figure 19, Overcurrent Comparator Functional Diagram
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Advanced Smart Battery Pack Controller
DISCHARGE LOGIC
MCLR 1 1 1 1 1 1 1 0
ODINT 0 0 0 0 0 0 1 X
CMPDISHI 0 0 0 0 0 1 X X
CMPDISSYSEN 0 1 1 1 1 X X X
CMPDISSYSPOL X 0 0 1 1 X X X
DETECT X 0 1 0 1 X X X
DIS Asserted Low Asserted Low Released High Released High Asserted Low Released High Released High Released High
Table 1, Overdischarge Logic Truth Table
CHARGE LOGIC
MCLR 1 1 1 1 1 1 1 0
OCINT 0 0 0 0 0 0 1 X
CMPCHGHI 0 0 0 0 0 1 X X
CMPCHGSYSEN 0 1 1 1 1 X X X
CMPCHGSYSPOL X 0 0 1 1 X X X
DETECT X 0 1 0 1 X X X
CHG Asserted Low Asserted Low Released High Released High Asserted Low Released High Released High Released High
Table 2, Overcharge Logic Truth Table
Using Software To Control The Protection MOSFETs
Although control of the Charge and Discharge Overcurrent MOSFETs is handled by the Overcurrent Protection Block, they can also be switched ON and OFF under software control. This is accomplished by writing to bits D0 and D3 of the CMPREG Register. Writing a `1' to either bit turns the respective protection MOSFET OFF, and writing a `0' turns it ON. Users should be aware that turning ON either of the protection MOSFETs under software control, can possibility cause a spurious ODI/OCI interrupt. Please use the following procedure when controlling the protection MOSFETs with software: 1. 2. 3. 4. Mask ODI/OCI interrupts. Turn ON the desired protection MOSFET. Clear ODI and OCI interrupt flags in INTRSTAT Register. Re-enable ODI/OCI interrupts.
Clearing Overcurrent Interrupts
Whenever the Overcurrent Protection Block turns OFF either the Charge or Discharge protection MOSFET, an interrupt is generated. Then the corresponding interrupt status bit (OCINT or ODINT) will be set in the INTRSTAT Register of the Interrupt Control Block. After each ODINT/OCINT event, the user should clear the respective interrupt status bit by writing a `1' to either bit D2 or bit D3 of the INTRSTAT Register.
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Advanced Smart Battery Pack Controller
CMPREG Register (Write Only ):
Bit D7 D6 D5 D4 D3 Name Unused Unused CMPCHGSYSEN CMPCHGSYSPOL CMPCHGHI POR 0 0 0 Function/Description
PORTB Address = 0x0A
D2 D1 D0
CMPDISSYSEN CMPDISSYSPOL CMPDISHI
0 0 0
See Tables 1 and 2 for functionality. See Tables 1 and 2 for functionality. 0 - Turns ON the Charge MOSFET and overcharge current comparator. 1 - Turns OFF the Charge MOSFET and overcharge current comparator. See Tables 1 and 2 for functionality. See Tables 1 and 2 for functionality. 0 - Turns ON the Discharge MOSFET and overdischarge current comparator. 1 - Turns OFF the Discharge MOSFET and overdischarge current comparator.
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Advanced Smart Battery Pack Controller
High-Voltage Output Port
Description
The High-Voltage Output Block gives the user the ability to switch high-voltage (up to BATT) nodes. Six outputs HV0 - HV5, can be asserted LOW to pull-down nodes normally tied HIGH (pulled-up to BATT). Two outputs HV6, and HV7, can be asserted HIGH to pull-up nodes normally tied LOW (pulled-down to AGND). All eight outputs are protected against ESD. The HV0 - HV5 pins are normally used to switch the battery pack capacity indicator LEDs ON and OFF. They could also be used to drive the external P-Channel MOSFETs of a charge balancing circuit.
BATT
R Peripheral Data Bus (8-bits) 8
High-Voltage Output Register
20% D7 D6 D5 D4 D3 D2 D1 D0 HV0 N 40%
HV1 N 60%
HV2 N 80%
HV3 N 100%
HV4 N
HV5 N
PULL DOWN
BATT
PNP HV6 PULL UP
PNP HV7 PULL UP
Figure 20, High-Voltage Output Port
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Advanced Smart Battery Pack Controller
Operation
Writing an 8-bit value to the block's HVO Register sets or clears the corresponding bit (HV0 - HV7), this in turn asserts or releases the corresponding High-Voltage Output pin (HV0 - HV7) of the port.
High-Voltage Output Port Register Description
HVO (Read/Write)
Bit D7 D6 D5 D4 D3 D2 D1 D0 Name HV7 HV6 HV5 HV4 HV3 HV2 HV1 HV0 POR 0 0 0 0 0 0 0 0 Function/Description 0 - Pin HV7 is high impedance. 1 - Pin HV7 is pulled up to BATT. 0 - Pin HV6 is high impedance. 1 - Pin HV6 is pulled up to BATT. 0 - Pin HV5 is high impedance. 1 - Pin HV5 is pulled to GND. 0 - Pin HV4 is high impedance. 1 - Pin HV4 is pulled to GND. 0 - Pin HV3 is high impedance. 1 - Pin HV3 is pulled to GND. 0 - Pin HV2 is high impedance. 1 - Pin HV2 is pulled to GND. 0 - Pin HV1 is high impedance. 1 - Pin HV1 is pulled to GND. 0 - Pin HV0 is high impedance. 1 - Pin HV0 is pulled to GND.
PORTB Address = 0x0B
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Advanced Smart Battery Pack Controller Digital Peripherals
High-Speed SPI Interface
Description
The MAX1780 uses the SPI Interface to read and write to an external SPI EEPROM. It can communicate with the latest technology 5MHZ EEPROMs using "turbo mode", or interface to the older generation 1MHz EEPROMs. With this architecture, the MAX1780 CPU can load program instructions/data from the serial EEPROM into its instruction RAM for execution. Once the block is configured, data is transferred through the SPI port by reading and writing to the SPIDATA register. Generation of the clock (SCLK) and data out (SO) signals is automatic, performed by the MAX1780 hardware.
8
SPICONFIG
8
PORTC Register
From Micro-Controller Core D7 D6 D5 D4 D3 D2 D1 D0
Counter + Logic Control
Peripheral Data Bus (8-bits)
Clock Generator + Mux
8-bit Shift Register
8 8
SPIDATA
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0
SCLK SO SI CS
Figure 21, High-Speed SPI Port
Operation
The SPICONFIG register needs to be set prior to any SPI operation. The POR value of this register is designed to allow normal operation of the MAX1780 IO pins IO2/SI, IO1/SO, and IO0/SCLK. The SPIENABLE bit of SPICONFIG must be set to a 1 for SPI operations. The speed needs to be selected via the SPISPEED bit, with 1 for Turbo Mode and 0 for Normal Mode. The MAX1780 SPI Interface is a Master, performing simultaneous read and write operations. As data is written to the IO1/SO pin, data is read into the IO2/SI pin. The data to be fed out serially the IO1/SO pin is written to the SPIDATA register. The input data returned via the serial port may be read from the same SPIDATA register.
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Advanced Smart Battery Pack Controller
Programs retrieving SPI data after a data transfer must wait 3 instruction cycles when the interface is in Turbo Mode, and 6 instruction cycles for Normal Mode. During this period, the MAX1780 CPU is free to execute other instructions. Because the SPI Interface shares use with the Port C IO[2:0] pins, the voltage levels are defined in the Logic Inputs/Outputs section of the Electrical Characteristics Table. Note that the SPI Chip Select timing is controlled using normal IO operation of pin IO3. User programs must enable/disable the SPI Chip Select as required.
SPI Interface Register Descriptions
SPIDATA Register (Read/Write):
Bit D7 D6 D5 D4 D3 D2 D2 D2 Name POR Function/Description Data bit 7 Data bit 6 Data bit 5 Data bit 4 Data bit 3 Data bit 2 Data bit 1 Data bit 0
PORTB Address = 0x0C
Note: Writing to this register causes data to be transferred on the SPI port and clocked through the shift register. Reading from this register causes no external events.
SPICONFIG (Read/Write ):
Bit D7 D6 D5 D4 D3 D2 D1 D0 Name POR 0 0 0 0 0 0 0 0
PORTB Address = 0x0D
Function/Description RFU (Always returns 0 if read) RFU (Always returns 0 if read) RFU (Always returns 0 if read) 0 - Normal Operation 1 - Factory Test Mode Only. RFU (Always returns 0 if read) RFU (Always returns 0 if read) 0 - Normal Mode (SCLK speed is INSTOSC/2) 1 - Turbo Mode (SCLK speed is INSTOSC). 0 - pins IO0/SCLK, IO1/SO, and IO2/SI have standard PORTC IO functionality. 1 - pins IO0/SCLK, IO1/SO, and IO2/SI have SPI Interface functionality.
BTEST
SPISPEED SPIENABLE
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Advanced Smart Battery Pack Controller
SMBus Interface
Introduction
The System Management Bus (SMBus) is a two wire, bi-directional serial bus which provides a simple, efficient interface for data exchange between devices. The SMBus uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. SMBus data is 8 bits in length. Data on the SMBus can be changed only when SCL is low and must be held stable when SCL is high. The MSB is transmitted first and each byte has to be followed by an acknowledge bit (ACK). An "ACKNOWLEDGE" is generated by the device receiving data by pulling the SDA line low on the 9th SCL clock cycle. Therefore one complete data byte transfer needs 9 SCL clocks. If the Master receiver does not acknowledge (NACK) the Slave transmitter after a byte has been transmitted, this signals an "end of data" to the Slave. The Slave will now release the SDA line allowing the Master to generate a "STOP" or "START" condition. A complete specification for the SMBus can be found in the System Management Bus Specification, Revision 1.1, December 11, 1998.
Features
* * * * * * * * * Master/Slave operation. Automatic SCL Hold. Two software programmable SMBus addresses. Four Master SCL clock frequencies. Completely Interrupt driven operation. Hardware Generation/Detection of SMBus START, Repeated START, and STOP conditions. SMBus Timeout Detector. Hardware Generation/Detection of the Acknowledge bit. Bus busy detection.
Description
The MAX1780 SMBus Interface can be completely interrupt driven. This allows the MAX1780 processor core to either sleep or process other tasks while the relatively slow SMBus transactions are handled. The MAX1780 factory ROM code includes many subroutines that automate the operation of the SMBus Interface. For a detailed description of these routines consult the MAX1780 ROM Code Supplement. The SMBus Interface is comprised of a transmitter and receiver and can function as both a Master and a Slave device. The Master transmitter can send SCL clocks at four user selectable speeds. The default Master SCL clock speed is 48.61 KHz. The Slave receiver can respond to two user programmable addresses at SCL clock speeds up to the full 100KHz specification. Once initialized, the Slave receiver will respond to SMBus communications to its address, even if the MAX1780 processor core is in SLEEP mode. Master mode operations require the MAX1780 instruction oscillator to be active to initiate START generation, byte operations, and STOP generation. The SMBus Interface incorporates separate receive and transmit data shift registers, allowing it to operate in full duplex. This means that as it transmits on the SMBus, it receives the data being transmitted. This allows the SMBus control software to compare data sent with data received. Similarly, all of the commands generated by the transmitter; START, STOP, ACK, etc. are detected. This allows software frame checking of the complete SMBus transaction.
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Advanced Smart Battery Pack Controller
8 PRIMADDR
7
ADDRESS COMPARE 8 SECDADDR
7
7
SCL RX SHIFT REGISTER 8
SCL IN SDA IN
PORT B PERIPHERAL BUS
8
SMBDATA 8
ADDRESS MATCHED
SCL OUT
H V
SDA
TX SHIFT REGISTER
SCL OUT SDA OUT
SDA OUT
H V
INT2
8
SLOV REGISTER 8 CONTROL LOGIC
STOP DETECTOR RESTART DETECTOR START DETECTOR 35msec TIMER ACK DETECTOR BUS IDLE DETECT
8
SMBSTATUS REGISTER
8
SMBMASK REGISTER
8
MASTER COMMAND SEQUENCER 8
8
SMBCONFIG REGISTER
Figure 22, SMBus Interface Block Diagram Start Detector
The Start Detector will set the STARTDET flag in the SMBSTATUS Register whenever a valid START condition, (a falling edge on SDA while SCL is high) occurs on the SMBus. If the STMSK bit in the SMBMASK Register is set, an interrupt (INT2) will be generated.
Restart Detector
The Restart Detector will set the RESTARTDET flag in the SMBSTATUS Register whenever a valid repeated Start condition (a falling edge on SDA while SCL is high and without a valid stop condition) occurs on the SMBus. If the REMSK bit in the SMBMASK Register is set, an interrupt (INT2) will be generated.
Stop Detector
The Stop Detector will set the STOPDET flag in the SMBSTATUS Register whenever a valid STOP condition (a raising edge on SDA while SCL is high) occurs on the SMBus. If the SPMSK bit in the SMBMASK Register is set, an interrupt (INT2) will be generated.
ACK Detector
The ACK Detector will set the ACKDET flag in the SMBSTATUS Register whenever a ACKNOWLEDGE th (SDA line is low at the rising edge of the 9 SCL clock) occurs on the SMBus. If the ACKMSK bit in the SMBMASK Register is set, an interrupt (INT2) will be generated.
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Advanced Smart Battery Pack Controller
ACK/NACK Generator
The ACK/NACK Generator's purpose is to assert the SDA line low after the falling edge of the 8th SCL clock and release the SDA line high after the falling edge of the 9th SCL clock. The ACK Generator is active in both Slave and Master Mode Receive operations, whenever the ACKNACK bit (D3) in the SMBCONFIG Register is reset to 0. There are two types of acknowledge pulses, Automatic and Conditional:
Automatic ACK Generation After a Start or Restart Condition:
The first 7 bits of captured data will be compared to the values programmed into both SMBus device address registers. If there was a match with either of them, the ACK Generator will generate an acknowledge pulse by asserting the SDA line.
Conditional ACK Generation In All Other Slave or Master Mode Receive Operations:
Reading the received data byte in the SMBDATA Latch releases the automatic SCL Hold.
SCL Holding Detector
The SMBus Master uses the SCL Holding Detector to monitor each low to high transition of the SCL line for the possibility that the Slave is holding it low.
Automatic SCL Hold Circuit
The purpose of the Automatic SCL Hold Circuit is to give the Slave a method for stretching the Master's SCL clock to allow it more time to get/give data being sent/requested by the Master. The Slave accomplishes this by asserting and holding the SCL line low after the Master transitions SCL from high to low after the falling edge of the 9th SCL clock following a Start or Restart condition. If the SCLHMSK bit is set, an interrupt will be generated to indicate the need to service the SMBDATA Register. To service a pending Send Byte Operation, the user writes a byte to the SMBDATA Register, which releases the SCL line high, and allows the Send Byte operation to continue. To service a pending Receive Byte Operation, the user reads a byte from the SMBDATA Register which releases the SCL line high.
Address Comparator
The purpose of the Address Comparator is to give the SMBus Peripheral a method for determining if communication on the SMBus is intended for it. After every Start or Restart condition, the first 7 bits of data shifted in on SDA are compared to the values stored in the PRIMADDR and SECDADDR Address Registers. If there is a match with either of the two address registers, bit D7 of the SMBSTATUS Register will be set accordingly: 0 - SECDADDR Address Matched 1 - PRIMADDR Address Matched If there is no match the SMBus control logic will reset to the Idle State.
Bus Idle Detector
The Bus Idle Detector monitors the levels of the SCL and SDA signals to determine the current condition of the SMBus. Essentially, this circuit is trying to determine if the SMBus is free of traffic. According to the System Management Bus Specification 1.1 the SMBus is free when SCL and SDA are high for a period greater than 50sec. If the Bus Idle Detector determines that the SCL and SDA signals have been high for a period greater than 50sec, it will set the BUSIDLE bit (D5) in the SLOV Register.
Master Clock Generator
The Master Clock Generator provides multiple clocks used by both the Transmitter and Receiver sections of the SMBus Block. It derives these clock signals from the core CPU's 3.5MHz instruction oscillator. During all Master operations and Slave send byte operations, the SMBus Interface requires the core CPU's 3.5MHz instruction oscillator. The SCL clock frequency can be programmed to operate at four different speeds by selecting bits D4 and D5 in the SMBCONFIG Register:
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Advanced Smart Battery Pack Controller
SMBCONFIG Divider Master SCL Frequency Ratio (Typical) D5 D4 0 0 fOSC/72 48.61 KHz 0 1 fOSC/168 20.83 KHz 1 0 fOSC/296 11.82 KHz 1 1 fOSC/488 7.17 KHz The POR default Master SCL clock speed is 48.61 kHz.
35msec Timer
The 35msec Timer monitors the time that the SCL clock line is held LOW. The timer begins running whenever SCL is LOW and resets when SCL returns HIGH. Should SCL remain LOW longer than 35msec, the SMBus Interface logic will set the TOUT status bit in the SMBSTAT Register, and generate an interrupt to the processor core. If the SCL line is not released HIGH, this interrupt will continue to occur each 35msec. This safety feature insures that the SMBus may be reset in the event a transmission is not completed. Should this feature not be desired, the user can disable it by clearing the TOUT mask bit (D5) in the SMBMASK Register.
Slave Mode Operation
Prior to operation, the User should enter values for both SMBus device addresses. When these addresses are set, the SMB Slave is ready to receive data independent of the MAX1780 processor core operation. The SMB status (STOP, START, RESTART) can be monitored in the SMBSTATUS register, as well as the ACK bein g detected. These signals will generate interrupts via INT2 if the appropriate SMBMASK bits are set. The SCL line is automatically held low after the Master sends the 9th clock pulse (Slave Acknowledge), and will not be released unless the SMBDATA Register is read from or written to by the MAX1780 processor core. The SMBus Interface has one address for the SMBDATA register, though there are actually two independent shift registers at the address (receive and transmit shift registers). The last valid data byte sent on the bus will always be in the SMBDATA register, though the microcontroller will only get the Acknowledge Interrupt if a matching address has been detected after the START was received. Writing to the SMBDATA address will load the transmit shift register, but not interfere with the data in the receive shift register.
Initialization
Update SMBSPEED[1:0] bits in the SMBCONFIG Register to select a SCL frequency. Default is 48.61 KHz. Set the CMD[2:0] bits in the SMBCONFIG Register to 111 (Slave Receive). Update the PRIMADDR and SECDADDR Address Registers to define the Slave device address. If both device addresses are not required, enter the same address in both registers.
Master Mode Operation
Master command operations are selected via the CMD[2:0] bits in the SMBCONFIG Register. These bits must be set prior to any master mode operation. Generally, a Master SMBus transaction will consist of a START signal followed by a Slave address byte, then a number of data bytes, and complete the operation with a STOP condition. The SCL clock is held low at the end of all master mode operations except for STOP. When any master mode operation is finished, the MSTDON bit will be set in the SMBSTATUS Register and provide an interrupt if the corresponding SMBMASK bit is set. The Master may receive data from the slave by writing a 0xFF byte (this will not corrupt data on the SMBus) and then reading the SMBDATA register once the operation is completed. The SMBus Interface can detect the SCL line extended low (clock stretching), and will pause the execution of the current Master operation until the SCL line is released high. At this time the Master will continue the last operation from where it was paused. If the SCL line is held low for longer than 35msec, the current Master operation will be terminated, the TOUT flag will be set in the SMBSTATUS Register, and an interrupt will be generated.
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Advanced Smart Battery Pack Controller
Master Mode operations require the MAX1780 Instruction Oscillator to be running in order to function properly. The user should insure that the OSLB bit in the OPTION Register is set to `1' so that the instruction oscillator will continue to run when the processor core is in SLEEP mode. This is only necessary for SMBus Master operations, where the MAX1780 must generate the SCL clock.
Sending a START Signal
A START signal is defined as a high to low transition of SDA while SCL is high. A START will be initiated only if both SDA and SCL have been high for a period exceeding 50uS. The following steps explain how to generate the START signal: 1. Set the CMD[2:0] bits in the SMBCONFIG Register to 0b000, a Send Start operation. 2. Perform a "dummy write" 0xFF to the SMBDATA Register. This triggers the Master operation. 3. Wait for interrupt 2 or poll the SMBSTAT Register until the MSTDON flag is set.
Sending the Slave Address and Data Direction Bit
The first data byte immediately after the START signal, or repeated START signal, contains the address of the Slave device. This is a seven bit long address followed by a data direction bit (R/W-bit). The R/W-bit tells the slave the desired direction of data transfer. Only a Slave device with a matched address will respond by sending back an acknowledge bit by pulling SDA low on the 9th clock cycle. The following steps explain how to send the first byte of data (slave address): 1. Set the CMD[2:0] bits in the SMBCONFIG Register to 0b100, a Send Byte operation. Also, set the ACK/NACK control bit D3 to `1' (NACK), so that the Slave Acknowledge can be detected. 2. Load the "W" Register with the Slave Address and Data Direction Bit to be moved to the SMBDATA Register. 3. Move the contents of the "W" Register to the SMBDATA Register. This triggers the Master operation. 4. Wait for interrupt 2 or poll the SMBSTAT Register until the MSTDON flag is set. 5. Check the SMBSTAT Register for ACKDET flag to be set, indicating a Slave Acknowledge. 6. Read back the byte from SMBDATA Register. 7. Check the byte sent for integrity.
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Advanced Smart Battery Pack Controller
Sending a STOP Signal
The master can terminate an SMBus transaction by generating a STOP signal. A STOP signal is defined as a low to high transition of SDA while SCL is at logical high. The following steps explain how a STOP condition is generated by the Master transmitter: 1. Set the CMD[2:0] bits in the SMBCONFIG Register to 0b010, a Send Stop operation. 2. Perform a "dummy write" of 0xFF to the SMBDATA Register. This triggers the Master operation. 3. Wait for interrupt 2 or poll the SMBSTAT Register until the MSTDON flag is set.
Sending a Repeated START Signal
A repeated START signal is used to generate a START signal without first generating a STOP signal to terminate the communication. This is used by the Master to indicate to the Slave device that the data direction will change (transmit/receive mode) without releasing the bus. A program example is shown below. 1. Set the CMD[2:0] bits in the SMBCONFIG Register to 0b011, a Send Restart operation. 2. Perform a "dummy write" of 0xFF to the SMBDATA Register. This triggers the Master operation. 3. Wait for interrupt 2 or poll the SMBSTAT Register until the MSTDON flag is set.
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Advanced Smart Battery Pack Controller
SMBus Interface Register Descriptions
SMBCONFIG Register (Read/Write):
Bit Name D7 D6 D5-D4 SMBSPEED[1:0]
PORTB Address = 0x00
D3
ACKNACK
D2-D0 CMD[2:0]
POR Function/Description 0 RFU 0 RFU 00 D5 D4 Divider SCL Units Ratio (Typ) 0 0 fOSC/72 48.61 KHz 0 1 fOSC/168 20.83 KHz 1 0 fOSC/296 11.82 KHz 1 1 fOSC/488 7.17 KHz 0 Master or Slave Mode: 0 = ACK the next byte sent. 1 = NACK the next byte sent. 000 Programs the Master Command Sequencer: 000 = Master Generate Start Condition 001 = Master Receive Byte 010 = Master Generate Stop Condition 011 = Master Generate Repeated Start Condition 100 = Master Send Byte 101 = Slave Send Byte 111 = Slave Receive
CLOCK GENERATOR
ACK/NACK GENERATOR
MASTER COMMAND SEQUENCER SMBSPEED[0] SMBSPEED[1] ACKNACK
CMD[2]
CMD[1]
D7
D6
D5
D4
D3
D2
D1
SMBCONFIG REGISTER
PORT B PERIPHERAL BUS
Figure 23, SMBus Configuration Register
8
CMD[0] D0
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Advanced Smart Battery Pack Controller
SMBSTATUS Register (Read/Write):
Bit D7 Name ADDRSTAT POR -
PORTB Address = 0X01
D6
SCLHOLD
0
D5
TOUT
0
D4
MSTDON
0
D3
ACKDET
0
D2 D1
STOPDET RESTARTDET
1 0
D0
STARTDET
0
Function/Description Only valid after receiving the first ACKNOWLEDGE of a valid address. 0 - Secondary Address Matched. 1 - Primary Address Matched. Master or Slave Mode: Set to 1 when SCL is held LOW after ACK. Auto clear at next Read/Write of SMBDATA operation or at POR. Master or Slave Mode: Set to 1 when SMBWDT timer exceeds the period (35mSec). Auto clear at next Read/Write of SMBDATA operation or at POR. Master Mode Only: Set to 1 at the end of Any Master command operation. Auto clear at next Read/Write of SMBDATA operation or at POR. Master or Slave Mode: Set to 1 when a valid acknowledge pulse is detected. Auto clear at next Read/Write of SMBDATA operation or at POR. Will be set to 1 each time a Stop Condition is detected on the SMBus. Write 1 to Clear this bit Will be set to 1 each time a Repeated Start Condition is detected on the SMBus. Write 1 to Clear this bit. Will be set to 1 each time a Start Condition is detected on the SMBus. Write 1 to Clear this bit.
Special Notes: * Bits D6 through D0 are routed to INT2 and controlled by the SMBMASK register. * * Bits D7 and D6 are bus monitor bits. They are not cleared or set except by the state of the SCL and SDL lines. Bits D2, D1, and D0 are set when a STOP, RESTART, or START condition occurs. They are cleared by writing to the SMBSTATUS register. If the bits are not cleared "promptly", it is possible to have mo re than one bit (D2, D1, D0) set at a time. The TOUT timer (bit D5) is running whenever the SCL pin is low in Slave Mode or a Master Mode transmit operation is in progress.
*
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Advanced Smart Battery Pack Controller
SMBMASK Register (Read/Write):
Bit D7 D6 Name SCLHMSK POR 0 0 Function/Description RFU Master or Slave Mode: 0 = Mask SCLHOLD interrupts. 1 = Enable SCLHOLD interrupts. Master or Slave Mode: 0 = Mask TOUT interrupts. 1 = Enable TOUT interrupts. Master Mode only: 0 = Mask MSTDON interrupts. 1 = Enable MSTDON interrupts. Master or Slave Mode: 0 = Mask ACK Detector interrupts. 1 = Enable ACK Detector interrupts. Slave Mode only: 0 = Mask STOP interrupts. 1 = Enable STOP interrupts. Slave Mode only: 0 = Mask RESTART interrupts. 1 = Enable RESTART interrupts. Slave Mode only: 0 = Mask START interrupts. 1 = Enable START interrupts.
PORTB Address = 0x02
D5
TOUTMSK
0
D4
MSTDONMSK
0
D3
ACKMSK
0
D2 D1
SPMSK REMSK
0 0
D0
STMSK
0
67
Advanced Smart Battery Pack Controller
INT2 ADDRESS COMPARE
35msec TIMER
ACK DETECT MASTER COMMAND SEQUENCER
STOP DETECT
RESTART DETECT
START DETECT RESTARTDET ADDRSTAT RESTARTMSK MSTDMSK STARTDET MSTDONE SCLHOLD STOPDET ACKDET TOUT
STOPMSK
SCLHMSK
TOUTMSK
STARTMSK
ACKMSK
SCL D0 SDA
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
SMBMASK REGISTER
SMBSTATUS REGISTER
8
PORT B PERIHERAL BUS
Figure 24, SMBus Status And Mask Registers
68
8
Advanced Smart Battery Pack Controller
SMBDATA Register (Read/Write):
Bit D7 D6 D5 D4 D3 D2 D1 D0 Name SMB_D7 SMB_D6 SMB_D5 SMB_D4 SMB_D3 SMB_D2 SMB_D1 SMB_D0 POR Function/Description SMBus Data Bit 7. SMBus Data Bit 6. SMBus Data Bit 5. SMBus Data Bit 4. SMBus Data Bit 3. SMBus Data Bit 2. SMBus Data Bit 1. SMBus Data Bit 0.
PORTB Address = 0x03
PRIMADDR Latch (Write Only):
PORTB Address = 0x04
Bit Name POR Function/Description D7 SMBADDR1_D7 SMBus Address #1 Bit 7. D6 SMBADDR1_D6 SMBus Address #1 Bit 6. D5 SMBADDR1_D5 SMBus Address #1 Bit 5. D4 SMBADDR1_D4 SMBus Address #1 Bit 4. D3 SMBADDR1_D3 SMBus Address #1 Bit 3. D2 SMBADDR1_D2 SMBus Address #1 Bit 2. D1 SMBADDR1_D1 SMBus Address #1 Bit 1. D0 SMBADDR1_D0 Not connected to Address Comparator Note: SMBADDR1 must be programmed before SMB slave mode operation will function.
SECDADDR Latch (Write Only):
PORTB Address = 0x05
Bit Name POR Function/Description D7 SMBADDR2_D7 SMBus Address #2 Bit 7. D6 SMBADDR2_D6 SMBus Address #2 Bit 6. D5 SMBADDR2_D5 SMBus Address #2 Bit 5. D4 SMBADDR2_D4 SMBus Address #2 Bit 4. D3 SMBADDR2_D3 SMBus Address #2 Bit 3. D2 SMBADDR2_D2 SMBus Address #2 Bit 2. D1 SMBADDR2_D1 SMBus Address #2 Bit 1. D0 SMBADDR2_D0 Not connected to Address Comparator Note: SMBADDR2 must be programmed before SMB slave mode operation will function.
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Advanced Smart Battery Pack Controller
SLOV Register (Read/Write):
Bit D7 D6 D5 D4 D3 D2 D1 D0 Name SCLSTAT SDASTAT BUSIDLE SCLFORCE SDAFORCE PANIC BUSY DETECT POR 0 0 0 0 0 0
PORTB Address = 0X06
Function/Description State of the SCL pin State of the SDA pin 1 = If both SCA and SCL have been high for 50s. Read Only 0 = SCL is controlled by the SMBus block circuitry. 1 = SCL is Asserted Low. 0 = SDA is controlled by the SMBus block circuitry. 1 = SDA is Asserted Low. PANIC button (Reset the SMB state machine, Write Only) Set by Master Mode hardware (Read Only). State of the pin (Read Only)
BUS IDLE DETECT
MASTER SEQUENCER
SCL
SCL
HV
SDA
SDA
HV SDAFORCE SCLFORCE
SDASTAT
SCLSTAT
BUSIDLE
PANIC
BUSY
DETECT
DETECT
D7
D6
D5
D4
D3
D2
D1
D0
SLOV REGISTER
PORT B PERIHERAL BUS
Figure 25, SMBus SLOV Register
70
8
Advanced Smart Battery Pack Controller Design And Applications Information
Interfacing With An External Serial EEPROM
The MAX1780 has been designed to directly interface with an external serial EEPROM. The high-speed SPI port can communicate with serial EEPROMs at SCLK frequencies of up to 4MHz. The MAX1780 typical operating circuit uses an 8K x 8, X25650 serial EEPROM capable of accepting a 4MHz SCLK signal. Figure 26 below shows how to interface a serial EEPROM to the MAX1780. Please refer to the latest X25650 data sheet, or to that of the selected serial EEPROM for detailed electrical specifications and proper operation.
13 3.4V 8 3 7 VCC WP CS HOLD SCLK X25650 SI SO VSS 4 35 1 6 5 2 R2 10K R1 10K 44 41 42 43 14
VDD VAA
MAX1780
IO3 IO0/SCLK IO1/SO IO2/SI
C1 0.1F
GND
Figure 26, External EEPROM Interface Schematic
Chip Select (CS\)
The Chip Select (CS ) signal may be any free GPIO pin on the MAX1780. The MAX1780 typical operating circuit however, makes use of IO3 for the CS signal. Connect the desired GPIO on the MAX1780 to the CS input pin of the EEPROM. Use a 10Kohm resistor from the CS pin to the EEPROM's VCC supply to pull the signal high. When CS is HIGH, the EEPROM is deselected and it's SO output pin is at high impedance.
Serial Clock (SCLK)
The Serial Clock controls the serial bus timing for data input and output. The MAX1780 has a dedicated output pin (IO0/SCLK) for SCLK and should be connected to the SCLK input pin of the EEPROM.
Serial Output (SO)
SO is a serial data output pin. The MAX1780 has a dedicated output pin (IO1/SO) and should be connected to the SI input pin of the serial EEPROM. During a write cycle, data is shifted out on this pin. Data from the MAX1780 SPI port is clocked out with the falling edge of SCLK.
Serial Input (SI)
SI is the serial data input pin. The MAX1780 has a dedicated input pin (IO2/SI) and should be connected to the SO output pin of the serial EEPROM. Data into the MAX1780 SPI port is latched by the rising edge of SCLK. Use a 10K ohm resistor from the SI pin to the EEPROM's VCC supply to pull the signal high.
71
Advanced Smart Battery Pack Controller
Properly Connecting Lithium Ion Cells
The MAX1780 can directly connect to 2, 3, and 4 series Lithium Ion cell configurations. Figure 27 shows how to properly connect each of the series cell combinations. Note that in all cases, the positive terminal of the top series cell must have a connection to the B4P pin.
Si4435DY M1 R6 470K U1 9 DIS R7
Si4435DY M2
Si4435DY M1 R6 470K R7
Si4435DY M2
Si4435DY M1 R6 470K R7
Si4435DY M2
470K 12 BATT 10 CHG B4P 21
470K 12 BATT 10 CHG B4P 21
U1 DIS 9
470K 12 BATT 10 CHG B4P 21 CELL #4
U1
9 DIS
B3P
22
B3P
22 CELL #3
B3P
22 CELL #3
B2P
23
B2P
CELL #2
23 CELL #2
B2P
23 CELL #2
B1P
24
B1P
CELL #1
24 CELL #1
B1P
24 CELL #1
MAX1780
BN CS+
25 27 R8 51 C1 0.1F R9 20m
MAX1780
BN CS+
25 27 R8 51 C1 0.1F R9 20m
MAX1780
BN CS+
25 27 R8 51 C1 0.1F R9 20m
CS-
26
CS-
26
CS-
26
AGND
AGND
AGND
2 Series Cells
3 Series Cells
4 Series Cells
Figure 27, Proper Series Cell Connections
Choosing The Current Sense Resistor (RCS)
For greatest accuracy, choose RCS to ensure that the product of the maximum current to be measured IMAX and RCS does not exceed 137.33mV. Calculate the proper sense-resistor value as follows:
R CS := V CS I MAX
where IMAX is the maximum current to be accurately measured. Use only surface-mount metal-film resistors; wire-wound resistors are too inductive to provide acceptable results. Be sure to consider power dissipation when choosing the current-sense resistor to avoid resistor self-heating.
Example
Given:
IMAX = 5 A VCS = 137.33 mV
Determining RCS :
RCS = VCS IMAX RCS = 0.027
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Advanced Smart Battery Pack Controller
Checking The RCS Power Dissipation:
PRCS = VCS
2
RCS
PRCS = 0.687W
Setting The Overcurrent Thresholds
Overcharge Threshold Set the current at which the voltage on CS+ exceeds the voltage on OCI with a voltage divider placed between VAA and AGND (see Typical Operating Circuit). To set the overcharge threshold, choose R1 in the 1M range and calculate R2 from:
R2 R1 V AA ICharge -1 R CS MAX
where VAA = 3.4V, ICharge MAX is the maximum allowable charging current, and RCS is the current sense resistor value. As an example, suppose we want to open up the charge protection MOSFET whenever charge currents exceed 5.4A;
Given: R1 = 1 M VAA = 3.4 V RCS = 0.02 R1 VAA ICharge -1 MAX RCS Choosing the closest common value: R2 = 33 K ICharge MAX = 5.4 A
R2
R2 = 32.807 K Checking: ICharge MAX = R2
RCS ( R1 + R2)
VAA
ICharge MAX = 5.431 A
73
Advanced Smart Battery Pack Controller
Overdischarge Threshold Set the current at which the ODI voltage falls below AGND with a voltage divider placed between VAA and BN (see Typical Operating Circuit). To set the overdischarge threshold, choose R3 in the 1M range then calculate R4 from:
R3
R4
IDischargeMAX RCS VAA
where VAA = 3.4V, IDischarge MAX is the maximum allowable discharging current, and RC S is the current sense resistor value. As an example, suppose we want to open up the discharge protection MOSFET whenever discharge currents exceed 6.5A;
Given: R3 = 1 M VAA = 3.4 V RCS = 0.02 IDischarge MAX = 6.5 A
R4
R3
IDischarge MAX RCS VAA
Choosing the closest common value: R4 = 39 K
R4 = 38.235 K Checking:
IDischarge MAX = VAA
(R3 RCS)
R4
IDischarge MAX = 6.63 A
74
Advanced Smart Battery Pack Controller
Handling Battery Insertion Surge Currents
When inserting a battery pack into a notebook computer, an initial surge current will flow to charge up the notebook power supply's input capacitors. This la rge current spike can trigger the overdischarge current comparator, which will open up the Discharge MOSFET. This event will produce a nuisance Overcurrent interrupt. Figure 28 shows the MAX1780 overdischarge current detection circuitry, and the resistive elements that determine ISURGE.
DISCHARGE MOSFET
VAA = 3.4V R DIS
MAX1780
ISURGE
CHARGE MOSFET
R1 R CHG
R3
OCI
CELL STACK
COMP
OVERCHARGE
S
Q
R BATT
COCI
ODI CODI
+
R Q
R2 VBATT
R4
CS+
NOTEBOOK POWER SUPPLY
R ESR RSENSE
COMP CS-
OVERDISCHARGE
S
Q
CI N
+
R Q
Figure 28, Overcurrent Comparator System Diagram
When the ISURGE current approaches its peak value, the voltage on the Overdischarge current comparator input ODI goes below ground. This will cause the Overdischarge current comparator to trip. To prevent this, connect a 100nF filter capacitor (CODI) from the ODI pin to AGND.
Handling Charger Connection Surge Currents
When connecting a charger to a deeply discharged battery p ack, a surge current will flow because of the extremely low impedance of the battery cells. This large current spike, if large enough, can trigger the overcharge current comparator, which will open up the Charge MOSFET. This event will produce a nuisance Overcurrent interrupt. When the current approaches its peak value, the voltage on the Overcharge current comparator input OCI goes below ground. This will cause the Overcharge current comparator to trip. To prevent this, connect a 100nF filter capacitor (COCI) from the OCI pin to the CS+ pin.
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Advanced Smart Battery Pack Controller
Improving Fuel Gauge Measurement Accuracy
Use The Correct Ground Layout
The MAX1780 Fuel Gauge is very accurate, however care should be taken in laying out the PCB signal lines to the CS+ and CS- pins. Improper layout will result in degraded Fuel Gauge performance. Figure 29 below shows the recommended PCB layout. Vias to the ground plane should never be connected to either of the Kelvin traces that run between the sense resistor to the CS+ and CS- pins.
High-Power Trace
48
47
46
45
44
43
42
41
40
39
38
1 2 3 4 5 6 7 8 9 10 11 12 CS+ CS-
37
36 35 34 33 32
MAX1780ECM
31 30
Minimize This Length
29 28 C1 27 26 25 R8
R9 Kelvin Connections
Put R8 and C1 as close as possible to the MAX1780
Filter The Current Sense Inputs
The high-power ground traces around the current sense resistor can be very noisy. This noise, if directly coupled to the Fuel Gauge will result in degraded performance. Therefore, place a 51 resistor between current sense resistor and CS+, and bypass CS+ to CS- with a 0.1F ceramic capacitor (see Figure 29). This creates a low pass filter that greatly reduces the noise at the CS+ and CS- pins. To minimize leakage errors due to finite traceto-trace resistance, place both filter components as close to the CS+ pin as possible.
13
Figure 29, Layout Recommendation For Current Sense Inputs
14
15
16
17
18
19
20
21
22
23
24
High-Power Trace; Connect Grounds Here
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Advanced Smart Battery Pack Controller
Connecting The SHDNPin
Connect the SHDN pin to the positive battery pack terminal through a 3Megohm resistor (R5), as shown in Figure 33, MAX1780 Application Circuit. R5 limits the current consumed by the MAX1780 in shutdown. Connect a signal diode D1 (Cathode) from the SHDN pin to the IO4 pin (Anode). Bypass the SHDN pin to AGND with a 0.1F capacitor. This reduces the charge injection caused by the Discharge MOSFET when it turns on.
Shutting Down The MAX1780 Under Software Control
Whenever the voltage on the SHDN pin is less than 0.4V, the MAX1780 is in Shutdown Mode. In shutdown, all CPU activity is stopped, the linear voltage regulator output (VAA) will be zero, and the MAX1780's current consumption will typically be less than 100A. This low power state is excellent for minimizing cell discharge when storing MAX1780 based battery packs for extended periods. The following text provides MAX1780 software programmers with a simple procedure for implementing shutdown under software control. Please refer to Figure 30 below, and insure that the SHDN pin is connected as shown. Note that for shutdown to function under software control, any charge source connected to PACK+ and PACK- must be removed. Users should develop their control software to continually measure individual cell voltages, and compare them with a defined minimum cell voltage threshold (VCELL(MIN)). For Lithium Ion cells, this is typically 2.5V. Should any cell's voltage drop below VCELL(MIN) for a specified number of measurement cycles, the user software should perform the following tasks to shutdown the MAX1780: 1. Open the Discharge protection MOSFET. 2. Tri-state the IO4 GPIO pin. Once the voltage on the SHDN pin has collapsed, the MAX1780 will shutdown. The MAX1780 will remain in this very low-power state until the startup procedure is followed.
DISCHARGE CHARGE Si4435DY DISCHARGE CHARGE Si4435DY
PACK+
Si4435DY
PACK+
M2
Si4435DY
M1 R6 470K OPEN THE DISCHARGE PROTECTION MOSFET R7 470K
M1 R6 470K R7 470K
M2
R5 3M
R5 3M
9 DIS 11 SHDN
D1 1N4148
12 BATT
10 CHG 21 B4P 22
CELL #4 D1 1N4148
9 DIS 11 SHDN 45 IO4
CELL #3
12 BATT
10 CHG 21 B4P 22 B3P
CELL #3 CELL #4
45 IO4 B3P
23 B2P
CELL # 2
23 B2P
TRI-STATE THE IO4 OUTPUT CELL # 2
MAX1780
C4 0.1F
24 B1P
CELL #1
MAX1780
24 B1P
CELL #1
25 BN CS+ 27
3.4V
V SHDN < 0.4V
RSENSE
C4 0.1F
25 BN CS+ 27
RSENSE
AGND 35
CS-
26 AGND 35
CS-
26
PACK+
PACK+
Step 1
Step 2
Figure 30, MAX1780 Software Shutdown Procedure
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Advanced Smart Battery Pack Controller
VBATT
>= 3.5V
DISCHARGE
CHARGE Si4435DY
PACK+
Si4435DY
M1 R6 470K R7 470K
M2
ICHARGE
R5 3M
9 DIS 11
D1 1N4148
12 BATT
10 CHG B4P 21
CELL #4
SHDN
45
IO4
B3P
22
CELL #3
CHARGER
C4 0.1F
B2P
23
CELL # 2
MAX1780
VSHDN
> 2.2V
24 B1P
CELL #1
BN CS+
25 27
RSENSE
AGND 35
CS-
26
PACK+
Figure 31, Shutdown Recovery Procedure
Starting Up The MAX1780 After Being Shutdown
First, an external charge source is applied to the PACK+ and PACK- terminals. Current will enter through the Discharge MOSFET's body diode allowing the voltage on the BATT pin (VBATT) to rise. Similarly, current will flow from the PACK+ terminal through the 3 Megohm dropping resistor allowing the voltage on the SHDN pin (VSHDN) to rise. When VSHDN rises above 2.2V, the MAX1780 will initiate a Power-On/Reset, turning on the Charge and Discharge MOSFETs. At this point, the user's system software should begin measuring each cell's voltage, and comparing their values with the defined minimum cell voltage threshold VCELL(MIN). If all of the cell voltages are greater than or equal to this threshold value, the IO4 pin should be set to a logic `1'. This effectively "props up" the SHDN pin. The external charge source may now be removed. Now, even if the Discharge or Charge MOSFETs should be opened, the logic level produced by IO4 will cause the voltage on SHDN pin to be high enough to keep the MAX1780 from shutting down. The user's software should continue to check individual cell voltages, and as long as all of the cells are greater than the minimum cell voltage VCELL(MIN), allow normal operation to continue.
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Advanced Smart Battery Pack Controller
Implementing An SBS-IF Safety Signal
In most SBS-IF compliant Smart Battery systems, a "Safety Signal" is used. This mechanism allows an independent communication path between the Smart Battery and the Smart Battery Charger to enhance the safety of the charging circuit. Essentially, the Safety Signal is connected to a circuit that provides three different resistances depending on the temperature of the battery pack. For a complete discussion of the Safety Signal implementation, please refer to the SBS-IF specifications for Smart Battery Chargers and Smart Batteries.
S
R2 10K R3 2.2K
MAX1780
R1 47K M2 2N7002
M1 2N7002
46
IO5
47
IO6
Figure 32, MAX1780 Safety Signal Circuit Figure 32 provides a circuit for generating the Safety Signal using the IO5 and IO6 pins on the MAX1780. User developed Software running on the MAX1780 continually measures battery pack temperature to obtain the "Temp" value. It is compared against two user adjustable thresholds, "Cold" and "Hot" to determine the "Pack State". The IO5 and IO6 output pins are then driven in accordance to the following table: Temperature Comparison Temp Hot Cold < Temp < Hot Temp Cold Pack State Hot Normal Cold IO5 0 1 0 IO6 1 0 0
Circuit Layout And Grounding
Good PC board layout is essential to achieving the specified fuel gauge and data acquisition performance characteristics. Good layout includes the use of a ground plane, appropriate component placement, and correct routing of traces using appropriate trace widths. Design the printed circuit board so that the analog and digital sections are separated and confined to different areas on the board. Join the analog ground (AGND) and digital ground (GND) planes at a single -point star ground. Refer to the MAX1780 evaluation kit for an example of proper PCB layout.
79
Advanced Smart Battery Pack Controller Pin Descriptions
PIN 1-8 NAME HV0-HV7 FUNCTION High Voltage I/O. Outputs are accessed via the HVO Register. The HV0 - HV5 pins are high voltage open drain outputs that pull down to GND. The HV6 and HV7 pins are high voltage open collector PNP outputs that pull up to BATT. Over Discharge MOSFET drive output. Controls the P-channel MOSFET that prevents the battery from being deep discharged. Can also be used to disconnect battery stack from its external terminals when the pack is not installed in the computer. Over Charge MOSFET drive output. Controls the P-channel MOSFET that prevents overcharge and also prevents fast charging when the battery is deeply discharged. Shutdown. High voltage shutdown input. +4V to +28V Supply input. Digital Supply Input. Connect to VAA for normal operation. +3.4V Linear Regulator Supply Output. Connect to VDD for normal operation and bypass with a 0.47F capacitor to AGND. Analog Ground. Digital Ground. 32kHz crystal oscillator input. 32kHz crystal oscillator input. Master Reset. Bypass with 10nF capacitor to GND. User analog input to ADC. Cell # 4 positive terminal. Cell # 3 positive terminal. Cell # 2 positive terminal. Cell # 1 positive terminal. Cell # 1 negative terminal. Kelvin current sense negative input for measuring battery current. Kelvin current sense positive input for measuring battery current. Over discharge threshold input. Over charge threshold input. Factory test input. Tie to GND. Factory test inputs. Tie to GND Edge-sensitive (rising or falling) interrupt input. It can be used to signal battery pack insertion to the CPU. SMBus Data Line. Open drain DMOS output and logic sense input that is protected from shorts to the battery. SMBus Clock Line. Open drain DMOS output and logic sense input that is protected from shorts to the battery. Not connected. Not connected. Factory test input.
9
DIS
10 11 12 13 14 15, 35 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31-33 34 36 37 38 39 40
CHG
SHDN BATT VDD
VAA AGND GND OSC1 OSC2
MCLR AIN B4P B3P B2P B1P BN CSCS+ ODI OCI BTEST BTM0-BTM2
DETECT SDA SCL N.C. N.C. EXTCLK
80
Advanced Smart Battery Pack Controller
41 42 43 44 45 46 47 48 IO0/SCLK IO1/SO IO2/SI IO3 IO4/TMRA IO5 IO6 IO7/INT1 GPIO Port C Bit D0 and when the SPI Interface is selected, functions as the SPI Master clock (SCLK) signal. GPIO Port C Bit D1 and when the SPI Interface is selected, functions as the SPI Master serial data output (SO) signal. GPIO Port C Bit D2 and when the SPI Interface is selected, functions as the SPI Master serial data input (SI) signal. GPIO Port C Bit D3. GPIO Port C Bit D4 and Timer A clock input. GPIO Port C Bit D5. GPIO Port C Bit D6. GPIO Port C Bit D7 and Interrupt 1 input
81
Advanced Smart Battery Pack Controller Detailed Operating Circuit
Si4435DY Si4435DY
+
R5 3M 3.4V
M1 R6 470K U1 9 DIS 11 R7 470K 12 BATT 10 CHG
M2
C7 100nF
R1 1M 1%
R3 1M 1%
SHDN IO4/TMRA OCI
B4P
21 CELL #4
D1
45
1N4148 29 28
B3P ODI N.C. N.C. B2P
22 CELL #3 23 CELL #2
R2 33K 1% CS+
C6 100nF R4 39K 1% CS+
38 C4 0.1F 39
AGND
34 37
DETECT B1P SCL
24 CELL #1
C D
R16 1M
36 BATT R17 1M R15 1K 20% 40% 60% 80% 100% LED1 LED2 LED3 LED4 LED5 5 20 3.4V 40 47 R14 470K DISPLAY CAPACITY 46 48 30 S1 31 32 33 R13 300 8 7 6 1 2 3 4
SDA
BN CS+
25 27 R8 51 R9 20m
HV7 HV6 HV5 HV0 HV1 HV2 HV3 OSC2 18 OSC1 17
MAX1780
CS26
C1 0.1F
AGND Y1 32.768KHz
HV4 AIN EXTCLK IO6 IO5 IO7/INT1 BTEST BTM0 BTM1 BTM2 AGND 15 GND 16 AGND 35
MCLR
19 C5 0.01F
VAA VDD
14 13 R11 10K R12 10K 1 6 5 2 CS SCLK SI SO VSS U2 4 C2
0.47F
3.4V
8 VCC WP HOLD 3 7 C3
0.1F
IO3 IO0/SCLK IO1/SO IO2/SI
44 41 42 43
S
X25650
Figure 33, MAX1780 Application Circuit
82
Advanced Smart Battery Pack Controller Absolute Maximum Ratings
VDD = VAA, AGND = GND, unless otherwise noted.
PIN HV[5:0], SHDN , BATT, B1P, B2P, B3P, B4P, SCL, SDA, and DETECT to GND VAA, VDD, and MCLR to GND OSC1, OSC2, OCI, ODI, BTEST, BTM[2:0], EXTCLK, IO[7:0] to GND CS+, AIN, and BN to GND CS- to GND AGND to GND, and VAA to VDD DIS, CHG, HV[7:6] to GND B3P, B2P, B1P to GND
MIN -0.3 -0.3 -0.3 -2 -1 -0.3 -0.3 -0.3
MAX 30 6 VDD+0.3 6 1 0.3 BATT+0.3 B4P +0.3
UNITS V V V V V V V V
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other condi tions beyond those indicated in the operational sections of the specifications in not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Electrical Characteristics
BATT=12V, AGND=GND=CS-=0V, VDD=VAA, SHDN =3.4V, C VAA =0.47 F, INSTOSC=OFF, 32.768kHz on OSC2 TA = 0C to +85C, unless otherwise noted.
PARAMETER CONDITIONS BATT LINEAR REGULATOR (VAA) Input Voltage Range Includes dropout operation Output Voltage 4V < BATT < 28V, 0 < ILOAD < 10mA VAA Leakage Current BATT = 0V, VAA = 3.4V Short Circuit Current VAA = 0V, 2.5V < BATT < 28V Linear Regulator, Power Fail, BATT = 3.4V and 32kHz Clock Supply Current in Drop-out Power Fail Warning Trip Level Falling VAA Hysteresis on rising VAA ( PFW ) Power On Reset Trip Level Rising VAA Hysteresis on falling VAA ( MCLR ) SUPPLY CURRENT (BATT) SHUTDOWN: SHDN < 0.4V Everything Off SLEEP: INSTOSC = OFF Linear Regulator, Power Fail, INSTOSC = ON and 32kHz Clock. FG + OD/OC: CPU RUNNING Linear Regulator, Power Fail, CPU SLEEP (INSTOSC=OFF) 32kHz Clock, Fuel Gauge, Precision Reference, OD/OC Comparators & MOSFET Drivers active.
MIN 3.5 3.2
TYP
MAX 28 3.6 1 120 150
UNITS V V mA mA A
3.4 0.1 40 24
15
2.91 2.62
3.0 46 2.7 41 0.001 22 330 0.72 93
3.09 2.78
V mV V mV A A A mA A
1 40 550 1.2 160
83
Advanced Smart Battery Pack Controller Electrical Characteristics (continued)
BATT=12V, AGND=GND=CS-=0V, VDD=VAA, SHDN =3.4V, C VAA =0.47 F, INSTOSC=OFF, 32.768kHz on OSC2 TA = 0C to +85C, unless otherwise noted.
PARAMETER SUPPLY CURRENT (BATT) AFE/ADC + FG + OD/OC: Linear Regulator, Power Fail, 32kHz Clock, Fuel Gauge, Precision Reference, OD/OC Comparators & MOSFET Drivers active. Cancellation Circuit Supply Current from B4P (Only present during ADC conversions).
CONDITIONS CPU RUNNING CPU SLEEP (INSTOSC=OFF)
MIN
TYP 1.4 0.82
MAX 2.4 1.3
UNITS mA mA
One cancellation circuit on. 15V applied to cancellation pin. Two cancellation circuits on. 15V applied to cancellation pins.
65 130
120 240
A A
FUEL GAUGE Input Voltage Offset Input Resistance CS+ to AGND Charge Coulomb-Counter VCS = 137.33mV Accumulation Rate Discharge Coulomb-Counter VCS = -137.33mV Accumulation Rate DATA ACQUISITION UNIT (Offset Cancellation Enabled) Conversion Time 11-Bit 13-Bit 15-Bit 16-Bit LSB Bit weight High Voltage = 20.48V Low Voltage = 5.12V Gain Accuracy at Full Scale VAA: Tested @VDD=VAA=BATT=3.4V BN, AIN: Tested @ BN/AIN to AGND=5.12V B1P through B4P referenced to BN Integral Non linearity (INL)
49,500 49,500
1 113 50,000 50,000
30 50,500 50,500
V k Counts/s Counts/s
4.5 17 66 132.95 312.50 78.126 -1 -1 0.8 4 1 1 0.8
ms
V % % % LSBs
84
Advanced Smart Battery Pack Controller Electrical Characteristics (continued)
BATT=12V, AGND=GND=CS-=0V, VDD=VAA, SHDN =3.4V, C VAA =0.47 F, INSTOSC=OFF, 32.768kHz on OSC2 TA = 0C to +85C, unless otherwise noted.
PARAMETER CONDITIONS DATA ACQUISITION UNIT (Offset Cancellation Enabled) Input Offset Voltage Input Voltage Range B1P through B4P referenced to AGND AIN, BN referenced to AGND Low Voltage Range: AIN, BN High Voltage Range: BN, B1P, B2P, B3P, B4P No input bias current cancellation. Input Bias Current with B4P = 20V, and ADC & Input Bias Cancellation B3P=B2P=B1P=15V (ON): referenced to AGND (B3P, B2P, B1P) Input Bias Current with B4P=B3P=B2P=B1P=20.48V ADC (OFF): referenced to AGND Input Bias Current with BN=AIN=5.12V ADC (OFF): referenced to AGND Common Mode Error: B4P=B3P=B2P=B1P=20.48V B4P-B3P, B3P-B2P, and referenced to AGND B2P-B1P Note: This error is proportional to the common mode voltage from AGND. ADC Cell Differential Voltage Measurement Accuracy: B3P to B4P B3P = 12.75V, B4P = 17V B2P to B3P B2P = 8.5V, B3P = 12.75V B1P to B2P B1P = 4.25V, B2P = 8.5V BN to B1P BN = 0V, B1P = 4.25V ON-CHIP TEMPERATURE SENSOR (Offset Cancellation Enabled) LSB bit weight Temperature Measurement Error Input Resistance to AGND with ADC (ON):
MIN
TYP 0.1
MAX 1 20.48 5.12
UNITS mV V V Meg Ohm Meg Ohm
-0.2 -2 0.5 2 1 4
1.8 7.2
30
nA
0 0 6 36
nA nA mV
-50 -50 -50 -50
0 0 0 0
0.0078125
+50 +50 +50 +50
mV mV mV mV K K
+/-4
85
Advanced Smart Battery Pack Controller Electrical Characteristics (continued)
BATT=12V, AGND=GND=CS-=0V, VDD=VAA, SHDN =3.4V, C VAA =0.47 F, INSTOSC=OFF, 32.768kHz on OSC2 TA = 0C to +85C, unless otherwise noted.
PARAMETER CONDITIONS MIN OVERCHARGE AND OVERDISCHARGE COMPARATORS ODI, OCI Input Offset Voltage -7 ODI, OCI Input Bias Current FET input comparators -1 ODI, OCI Comparator 20mV input overdrive 3 Propagation Delay DIS, CHG Sink Current DIS, CHG = 2V 20 DIS, CHG Sink Current DIS, CHG = 20V, BATT = 20V 30 DIS, CHG Source Current 0V < DIS, CHG < BATT-2V 4 Leakage Current DIS = CHG = 28V INSTRUCTION OSCILLATOR Frequency 3 -40C to +85C, and 2.8V < VDD < 3.6V Temperature Variation -40C to +85C Supply Sensitivity 2.8V < VDD < 3.6V 32KHZ TIMER OSCILLATOR OSC1 Input Current OSC1=0V or 3.4V, OSC2 is floating OSC2 Sink Current OSC1= OSC2 = 3.4V 4 OSC2 Source Current OSC1= OSC2=0V 3 Transconductance 1.3 LOGIC INPUTS/OUTPUTS IO[7:0] Input Voltage Low IO[7:0] Input Voltage High 2.4 IO[7:0] High Impedance I/O pins programmed to Hi-Z. Leakage Current IO[7:0] Output Voltage Low ISINK = 2mA IO[7:0] Output Voltage High ISOURCE = 2mA VDD-0.6
MCLR RESET PIN MCLR Output Voltage Low MCLR Output Voltage High MCLR Pull-up Resistance MCLR Input High Voltage MCLR Input Low Voltage MCLR Input Hysterisis
TYP
MAX 7 1 30 80 100
UNITS mV A s A A mA A MHz % % nA A A A/V V V A V V V V
12 1 3.5 -2 2.4 125 10 7 5 4
8 500 20 20 12 0.8
0
1 0.4
ISINK = 1mA, and BATT = VAA = VDD = 2.5V ISOURCE = 0 BATT = VAA = VDD = 3.4V Internally connected from MCLR to VDD.
0.4
VDD 0.2
10 2.4
20
40
k V
1 250
V mV
86
Advanced Smart Battery Pack Controller Electrical Characteristics (continued)
BATT=12V, AGND=GND=CS-=0V, VDD=VAA, SHDN =3.4V, C VAA =0.47 F, INSTOSC=OFF, 32.768kHz on OSC2 TA = 0C to +85C, unless otherwise noted.
PARAMETER CONDITIONS HIGH-VOLTAGE LOGIC INPUT (DETECT) DETECT Input High Voltage DETECT Input Low Voltage DETECT VDETECT = 28V Output High Leakage Current SHUTDOWN PIN LOGIC LEVELS (SHDN ) Input High Voltage Input Low Voltage Input Bias Current SHDN = 3.6V
MIN 2.1
TYP
MAX
UNITS V
0.8 1
V A
2.2 0.8 0.4 2.0
V V A A V A V A
18 50 SHDN = 28V HIGH-VOLTAGE OPEN DRAIN OUTPUTS THAT PULL TO GND (HV0-HV5) Output Voltage Low ISINK = 7 mA 1.4 Leakage Current Output High, VAPPLIED = 28V 1 HIGH-VOLTAGE OPEN COLLECTOR OUTPUTS THAT PULL TO BATT (HV6 and HV7) Output Voltage High ISOURCE = 100A BATT0.5 Leakage Current HV6 = HV7 = 0V 1
87
Advanced Smart Battery Pack Controller SPI Interface Electrical Characteristics
tCP VOH tCH tCL
SCLK
VO L
tDO VOH
SO
VOL
DATA OUT
DATA OUT
DATA OUT
tDS tDH
SI
VIH VIL
DATA IN
DATA IN
DATA IN
Figure 34, SPI Interface Timing
BATT=12V, AGND=GND=CS-=0V, VDD=VAA, SHDN =3.4V, C VAA =0.47 F, INSTOSC=OFF, 32.768kHz on OSC2 TA = 0C to +85C, unless otherwise noted.
SYMBOL PARAMETER/CONDITIONS SPI INTERFACE AC TIMING (CLOAD = 20pF) tCP SCLK Period tCH SCLK Pulse Width High tCL SCLK Pulse Width Low tDO SCLK Fall to SO Valid tDS SI to SCLK Data Setup Time tDH SI to SCLK Data Hold Time SPI INTERFACE DC CHARACTERISTICS VOH SPI Output High; ISOURCE = 2mA VOL VIH VIL SPI Output Low; ISOURCE = 2mA SPI Input High SPI Input Low
MIN 250 100 100 -30 70 0
VDD0.6
TYP
MAX
UNITS ns ns ns ns ns ns V
30
0.4 2.4 0.8
V V V
88
Advanced Smart Battery Pack Controller SMBus Interface Electrical Characteristics
tLOW V IH tR tF
SCL
VIL tHIGH
t HD:STA
t HD:DAT
tSU:DAT
t SU:STA
tSU:STO
V IH
SDA
VIL tBUF
P
S
S
P
Figure 35, SMBus Timing Diagram
BATT=12V, AGND=GND=CS-=0V, VDD=VAA, SHDN =3.4V, C VAA =0.47 F, INSTOSC=OFF, 32.768kHz on OSC2 TA = 0C to +85C, unless otherwise noted.
SYMBOL PARAMETER/CONDITIONS Slave Operation tBUF Bus free time between a Stop and Start condition. tHD:STA Hold time after a (Repeated) Start condition. tSU:STA Repeated Start setup time. tSU:STO Stop condition setup time. tHD:DAT Transmit Data hold Receive time. tSU:DAT Receive Data setup time. tTIMEOUT Detect clock (SCL) low timeout. tLOW Clock (SCL) low period. tHIGH Clock (SCL) high period.
MIN 4.7 4.0 4.7 4.0 300 0 250
TYP
MAX
UNITS s s s s ns ns ns
35 4.7 4.0
ms s s
89
Advanced Smart Battery Pack Controller
BATT=12V, AGND=GND=CS-=0V, VDD=VAA, SHDN =3.4V, C VAA =0.47 F, INSTOSC=OFF, 32.768kHz on OSC2 TA = 0C to +85C, unless otherwise noted.
SYMBOL PARAMETER/CONDITIONS All Master Operations tTIMEOUT Detect clock (SCL) low timeout. Master Operation (SMBSPEED bits = 00) fSCL SCL clock frequency. tHD:STA Hold time after a (Repeated) Start condition. tSU:STA Repeated Start setup time. tSU:STO Stop condition setup time. tHIGH SCL High Period tLOW SCL Low Period tHD:DAT Master Transmit Data hold Master Receive time. Master Acknowledge tSU:DAT Master Transmit Data setup Master Receive time. Master Acknowledge Master Operation (SMBSPEED bits = 01) fSCL SCL clock frequency. tHD:STA Hold time after a (Repeated) Start condition. tSU:STA Repeated Start setup time. tSU:STO Stop condition setup time. tHIGH SCL High Period tLOW SCL Low Period tHD:DAT Master Transmit Data hold Master Receive time. Master Acknowledge tSU:DAT Master Transmit Data setup Master Receive time. Master Acknowledge Master Operation (SMBSPEED bits = 10) fSCL SCL clock frequency. tHD:STA Hold time after a (Repeated) Start condition. tSU:STA Repeated Start setup time. tSU:STO Stop condition setup time. tHIGH SCL High Period tLOW SCL Low Period tHD:DAT Master Transmit Data hold Master Receive time. Master Acknowledge tSU:DAT Master Transmit Data setup Master Receive time. Master Acknowledge
90
MIN
TYP
MAX 35
UNITS ms KHz s s s s s s ns ns s ns s KHz s s s s s s ns ns s ns s KHz s s s s s s ns ns s ns s
42.2 8.2 19.7 8.2 8.7 8.7 4.2 0 300 4.2 250 8.7 17.96 20.2 49.7 20.2 20.7 20.7 10.2 0 300 10.2 250 20.7 10.17 36.2 89.7 36.2 36.7 36.7 18.2 0 300 18.2 250 36.7
48.6 9.7 22.9 9.7 10.3 10.3 5.1
56.5 11.6 27 11.6 12.3 12.3 6.3
5.1 10.3 20.83 23.4 57.1 23.4 24 24 12
6.3 12.3 23.81 27.6 67 27.6 28.3 28.3 14.3
12 24 11.82 41.7 102.9 41.7 42.3 42.3 21.1
14.3 28.3 13.56 49 120.3 49 49.6 49.6 25
21.1 42.3
25 49.6
Advanced Smart Battery Pack Controller
Master Operation (SMBSPEED bits = 11) fSCL SCL clock frequency. tHD:STA Hold time after a (Repeated) Start condition. tSU:STA Repeated Start setup time. tSU:STO Stop condition setup time. tHIGH SCL High Period tLOW SCL Low Period tHD:DAT Master Transmit Data hold Master Receive time. Master Acknowledge tSU:DAT Master Transmit Data setup Master Receive time. Master Acknowledge 6.16 60.2 149.7 60.2 60.7 60.7 30.2 0 300 30.2 250 60.7 7.17 69.1 171.4 69.1 69.7 69.7 34.9 8.19 81 200.3 81 81.6 81.6 41 KHz s s s s s s ns ns s ns s
34.9 69.7
41 81.6
Table 3, SMBus AC Characteristics
BATT=12V, AGND=GND=CS-=0V, VDD=VAA, SHDN =3.4V, C VAA =0.47 F, INSTOSC=OFF, 32.768kHz on OSC2 TA = 0C to +85C, unless otherwise noted.
SYMBOL VIL VIH SCL and SDA Output Low Voltage SCL and SDA Output High Leakage Current SCL and SDA short circuit current limit
PARAMETER/CONDITIONS Clock/Data input low voltage. Clock/Data input high voltage. ISINK = 2mA
MIN 0.8
TYP
MAX 2.1 0.4
UNITS V V V
VSCL = VSDA= 28V
1
A
VSCL = VSDA= 28V
6
50
mA
Table 4, SMBus DC Characteristics
91
Advanced Smart Battery Pack Controller Electrical Characteristics (continued, TA = -40C to +85C)
BATT=12V, AGND=GND=CS-=0V, VDD=VAA, SHDN =3.4V, C VAA =0.47 F, INSTOSC=OFF, 32.768kHz on OSC2 TA = -40C to +85C, unless otherwise noted.
PARAMETER CONDITIONS MIN BATT LINEAR REGULATOR (VAA) Input Voltage Range Includes dropout operation 3.5 Output Voltage 4V < BATT < 28V, 0 < ILOAD < 3.2 10mA Short Circuit Current VAA = 0V, 15 2.5V < BATT < 28V Power Fail Warning Trip Level Falling VAA 2.91 (PFW\) Power On Reset Trip Level Rising VAA 2.62 ( MCLR ) SUPPLY CURRENT (BATT) SHUTDOWN: SHDN < 0.4V Everything Off ON-CHIP TEMPERATURE SENSOR Temperature Measurement Error OVERCHARGE AND OVERDISCHARGE COMPARATORS ODI, OCI Input Offset Voltage -7 ODI, OCI Input Bias Current FET input comparators -1 ODI, OCI Comparator 20mV input overdrive Propagation Delay DIS, CHG Sink Current DIS, CHG = 2V 20 DIS, CHG Sink Current DIS, CHG = 20V, BATT = 20V 30 DIS, CHG Source Current 0V < DIS, CHG < BATT-2V 3 Leakage Current DIS = CHG = 28V INSTRUCTION OSCILLATOR Frequency 3 -40C to +85C, and 2.8V < VDD < 3.6V 32KHZ TIMER OSCILLATOR OSC1 Input Current OSC1=0V or 3.4V, OSC2 is floating OSC2 Sink Current OSC1= OSC2 = 3.4V 4 OSC2 Source Current OSC1= OSC2=0V 3 Transconductance 1.3 LOGIC INPUTS/OUTPUTS IO[7:0] Input Voltage Low IO[7:0] Input Voltage High 2.4 IO[7:0] High Impedance I/O pins programmed to Hi-Z. Leakage Current IO[7:0] Output Voltage Low ISINK = 2mA IO[7:0] Output Voltage High ISOURCE = 2mA VDD-0.6
TYP
MAX 28 3.6 120 3.09 2.78
UNITS V V mA V V
1
A
+/-8
K
7 1 30 80 100 1 4
mV A s A A mA A MHz
500 20 20 12 0.8 1 0.4
nA A A A/V V V A V V
92
Advanced Smart Battery Pack Controller Electrical Characteristics (continued, TA = -40C to +85C)
BATT=12V, AGND=GND=CS-=0V, VDD=VAA, SHDN =3.4V, C VAA =0.47 F, INSTOSC=OFF, 32.768kHz on OSC2 TA = -40C to +85C, unless otherwise noted.
PARAMETER
MCLR RESET PIN MCLR Output Voltage Low MCLR Output Voltage High MCLR Input High Voltage MCLR Input Low Voltage
CONDITIONS ISINK = 1mA, and BATT = VAA = VDD = 2.5V ISOURCE = 0 BATT = VAA = VDD = 3.4V
MIN
TYP
MAX 0.4
UNITS V V V
VDD 0.2 2.4 1 2.2 0.4 3.0 60
V V V A A V A V A
SHUTDOWN PIN LOGIC LEVELS (SHDN ) Input High Voltage Input Low Voltage Input Bias Current SHDN = 3.4V
SHDN = 28V HIGH-VOLTAGE OPEN DRAIN OUTPUTS THAT PULL TO GND (HV0-HV5) Output Voltage Low ISINK = 1 mA 0.4 Leakage Current Output High, VAPPLIED = 28V 1 HIGH-VOLTAGE OPEN COLLECTOR OUTPUTS THAT PULL TO BATT (HV6 and HV7) Output Voltage High ISOURCE = 100A BATT0.5 Leakage Current Output Low VAPPLIED = 0V 1
93
Advanced Smart Battery Pack Controller SPI Interface Electrical Characteristics (TA = -40C to +85C)
tCP VOH tCH tCL
SCLK
VO L
tDO VOH
SO
VOL
DATA OUT
DATA OUT
DATA OUT
tDS tDH
SI
VIH VIL
DATA IN
DATA IN
DATA IN
Figure 36, SPI Interface Timing (T A = -40C to +85C)
BATT=12V, AGND=GND=CS-=0V, VDD=VAA, SHDN =3.4V, C VAA =0.47 F, INSTOSC=OFF, 32.768kHz on OSC2 TA = -40C to +85C, unless otherwise noted.
SYMBOL PARAMETER/CONDITIONS SPI INTERFACE AC TIMING (CLOAD = 20pF) tCP SCLK Period tCH SCLK Pulse Width High tCL SCLK Pulse Width Low tDO SCLK Fall to SO Valid tDS SI to SCLK Data Setup Time tDH SI to SCLK Data Hold Time SPI INTERFACE DC CHARACTERISTICS VOH SPI Output High; ISOURCE = 2mA VOL VIH VIL SPI Output Low; ISOURCE = 2mA SPI Input High SPI Input Low
MIN 250 100 100 -30 70 0 VDD0.6
TYP
MAX
UNITS ns ns ns ns ns ns V
30
0.4 2.4 0.8
V V V
94
Advanced Smart Battery Pack Controller SMBus Interface Electrical Characteristics (TA = -40C to +85C)
tLOW V IH tR tF
SCL
VIL tHIGH
t HD:STA
t HD:DAT
tSU:DAT
t SU:STA
tSU:STO
V IH
SDA
VIL tBUF
P
S
S
P
Figure 37, SMBus Timing Diagram (T A = -40C to +85C)
BATT=12V, AGND=GND=CS-=0V, VDD=VAA, SHDN =3.4V, C VAA =0.47 F, INSTOSC=OFF, 32.768kHz on OSC2 TA = -40C to +85C, unless otherwise noted.
SYMBOL PARAMETER/CONDITIONS Slave Operation tBUF Bus free time between a Stop and Start condition. tHD:STA Hold time after a (Repeated) Start condition. tSU:STA Repeated Start setup time. tSU:STO Stop condition setup time. tHD:DAT Transmit Data hold Receive time. tSU:DAT Transmit Data setup Receive time. tTIMEOUT Detect clock (SCL) low timeout. tLOW Clock (SCL) low period. tHIGH Clock (SCL) high period.
MIN 4.7 4.0 4.7 4.0 300 0 250 250
TYP
MAX
UNITS s s s s ns ns ns ns
35 4.7 4.0
ms s s
95
Advanced Smart Battery Pack Controller
BATT=12V, AGND=GND=CS-=0V, VDD=VAA, SHDN =3.4V, C VAA =0.47 F, INSTOSC=OFF, 32.768kHz on OSC2 TA = -40C to +85C, unless otherwise noted.
SYMBOL PARAMETER/CONDITIONS All Master Operations tTIMEOUT Detect clock (SCL) low timeout. Master Operation (SMBSPEED bits = 00) fSCL SCL clock frequency. tHD:STA Hold time after a (Repeated) Start condition. tSU:STA Repeated Start setup time. tSU:STO Stop condition setup time. tHIGH SCL High Period tLOW SCL Low Period tHD:DAT Master Transmit Data hold Master Receive time. Master Acknowledge tSU:DAT Master Transmit Data setup Master Receive time. Master Acknowledge Master Operation (SMBSPEED bits = 01) fSCL SCL clock frequency. tHD:STA Hold time after a (Repeated) Start condition. tSU:STA Repeated Start setup time. tSU:STO Stop condition setup time. tHIGH SCL High Period tLOW SCL Low Period tHD:DAT Master Transmit Data hold Master Receive time. Master Acknowledge tSU:DAT Master Transmit Data setup Master Receive time. Master Acknowledge Master Operation (SMBSPEED bits = 10) fSCL SCL clock frequency. tHD:STA Hold time after a (Repeated) Start condition. tSU:STA Repeated Start setup time. tSU:STO Stop condition setup time. tHIGH SCL High Period tLOW SCL Low Period tHD:DAT Master Transmit Data hold Master Receive time. Master Acknowledge tSU:DAT Master Transmit Data setup Master Receive time. Master Acknowledge
96
MIN
TYP
MAX 35
UNITS ms KHz s s s s s s ns ns s ns s KHz s s s s s s ns ns s ns s KHz s s s s s s ns ns s ns s
42.2 8.2 19.7 8.2 8.7 8.7 4.2 0 300 4.2 250 8.7 17.96 20.2 49.7 20.2 20.7 20.7 10.2 0 300 10.2 250 20.7 10.17 36.2 89.7 36.2 36.7 36.7 18.2 0 300 18.2 250 36.7
56.5 11.6 27 11.6 12.3 12.3 6.3
6.3 12.3 23.81 27.6 67 27.6 28.3 28.3 14.3
14.3 28.3 13.56 49 120.3 49 49.6 49.6 25
25 49.6
Advanced Smart Battery Pack Controller
Master Operation (SMBSPEED bits = 11) fSCL SCL clock frequency. tHD:STA Hold time after a (Repeated) Start condition. tSU:STA Repeated Start setup time. tSU:STO Stop condition setup time. tHIGH SCL High Period tLOW SCL Low Period tHD:DAT Master Transmit Data hold Master Receive time. Master Acknowledge tSU:DAT Master Transmit Data setup Master Receive time. Master Acknowledge 6.16 60.2 149.7 60.2 60.7 60.7 30.2 0 300 30.2 250 60.7 8.19 81 200.3 81 81.6 81.6 41 KHz s s s s s s ns ns s ns s
41 81.6
Table 5, SMBus AC Characteristics (T A = -40C to +85C)
BATT=12V, AGND=GND=CS-=0V, VDD=VAA, SHDN =3.4V, C VAA =0.47 F, INSTOSC=OFF, 32.768kHz on OSC2 TA = -40C to +85C, unless otherwise noted.
SYMBOL VIL VIH SCL and SDA Output Low Voltage SCL and SDA Output High Leakage Current SCL and SDA short circuit current limit
PARAMETER/CONDITIONS Clock/Data input low voltage. Clock/Data input high voltage. ISINK = 2mA
MIN 0.8
TYP
MAX 2.1 0.4
UNITS V V V
VSCL = VSDA= 28V
1
A
VSCL = VSDA= 28V
6
50
mA
Table 6, SMBus DC Characteristics (T A = -40C to +85C)
97
Advanced Smart Battery Pack Controller
Typical Operating Characteristics
(TA = +25C, unless otherwise noted)
35 30 TOP CELL MEASUREMENT ERROR (mV) 25 20
TRIM POINT @ +25C
TYPICAL LITHIUM ION CELL OPERATING ZONE
15 10 5 0 -5 -10 -15 -20 -25 -30 -35 -40 -30 -20 -10 0 10 20 30 40 TEMPERATURE (C) 50 60
MAX
AVG
MIN
70
80
Figure 38, Typical ADC Voltage Measurement Error
98
Advanced Smart Battery Pack Controller
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted)
22 20 18 16 14 IBIAS (A) 12 10 8 6 4 2 0 0 5 10 15 VSHDN (Volts) 20 25 30
Figure 39, SHDN Input Bias Current vs. VSHDN
3.42 0A
3.40
3.38 VAA (Volts)
100A
3.36 1mA 3.34 10mA 3.32
3.30
3.28 -40
-30
-20
-10
0
10
20
30
40
50
60
70
80
TEMPERATURE (C)
Figure 40, VAA Output Voltage vs. Load Current and Temperature
99
Advanced Smart Battery Pack Controller
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted)
2
CHARGE COUNT INCREMENTED
1 FREQUENCY (Hz)
0
INPUT VOLTAGE OFFSET
OUTPUT FREQUENCY OFFSET
-1
DISCHARGE COUNT INCREMENTED
-2 -5.00
-3.75
-2.50
-1.25
0.00
1.25
2.50
3.75
5.00
INPUT VOLTAGE (V)
Figure 41, Fuel Gauge Frequency vs. Input Voltages Near Zero
100
75
50 FREQUENCY (KHz)
CHARGE COUNT INCREMENTED
FULL SCALE CHARGE +133.7mV
25
0
-25
-50
FULL SCALE DISCHARGE -133.7mV
DISCHARGE COUNT INCREMENTED
-75
-100 -240
-180
-120
-60
0
60
120
180
240
INPUT VOLTAGE (mV)
100
Advanced Smart Battery Pack Controller
Figure 42, Fuel Gauge Frequency vs. Input Voltage
0.5
0.4
FULL SCALE DISCHARGE -133.7mV
GAIN ERROR (%)
0.3 DISCHARGE COULOMB COUNTER
0.2
0.1
0.0
-0.1 -180
-150
-120
-90 INPUT VOLTAGE (mV)
-60
-30
0
Figure 43, Discharge Gain Error vs. Fuel Gauge Input Voltage
0.5
0.4
FULL SCALE CHARGE +133.7mV
GAIN ERROR (%)
0.3
0.2 CHARGE COULOMB COUNTER
0.1
0.0
-0.1
0
30
60
90 INPUT VOLTAGE (mV)
120
150
180
Figure 44, Charge Gain Error vs. Fuel Gauge Input Voltage
101
Advanced Smart Battery Pack Controller Package Information
102
Advanced Smart Battery Pack Controller Appendix
An Overview Of Smart Batteries
Over the past five years, Smart Batteries, incorporating Lithium Ion cells, have evolved as the industry standard for supplying power to notebook computers. Smart Batteries vary widely in their exact composition, however common to all is their integration of rechargeable cells capable of providing power, with electronic measurement and control circuitry. Some Smart Batteries, depending on the cell chemistry used, also have electronic circuitry to protect the battery cells from being destroyed by either the battery charger or the notebook computer.
The Smart Battery In A Notebook Power Supply System
Figure 45 illustrates a typical notebook computer power supply system. Note that the Smart Battery can communicate with other devices, such as the Host Computer, or Smart Battery Charger, via two separate communication interfaces. The primary communication interface, the System Management Bus (SMBus), is a two wire, bi-directional serial bus that provides a simple, efficient interface for data exchange between devices. The SMBus uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. Using the SMBus, the Smart Battery can provide data when requested, send charging information to a charger, and broadcast critical alarm information when parameters (measured or calculated) exceed predetermined limits within the particular battery system.
AC
WALL CUBE
DCIN
SMART BATTERY CHARGER
S D C
+ -
DC/DC POWER SUPPLY
+ COMPUTER & LOAD
C D
HOST
SMBus
Safety Signal
+
S
C
D
-
SMART BATTERY #1
Figure 45, Simplified Notebook Computer Power Supply System
In the power supply system described by Figure 45, the Smart Battery can be both a Slave and a Master SMBus device. When responding to requests from the Host computer, it is a Slave device. When it broadcasts charge current and voltage requirements to the Smart Charger, it is an SMBus Master device. Note that there is a single line Safety Signal that is connected between the Smart Battery and the Smart Charger. It communicates the Smart
103
Advanced Smart Battery Pack Controller
Battery's gross temperature (COLD, NORMAL, and HOT), and the Smart Charger then terminates or inhibits charge, depending on the temperature information sent. The Safety Signal is also an alternate signaling method should the SMBus interface become inoperable. Battery chargers often use the "S" Pin to confirm correct charging.
What Makes Smart Batteries "Smart"?
Most Smart or Intelligent Battery systems not only calculate real-time parametric data, they also predict battery performance based on given load conditions. The ability to provide predictive performance information makes them truly smart. The Smart Battery also stores portions of measured data to maintain a historical record of operation. This historical battery data is stored in non-volatile memory device such as an EEPROM. By storing this historical data in EEPROM, the Smart Battery can maintain its capacity information even when being moved from one notebook computer to another.
Lithium Ion Cell Protection
In Smart Battery packs designed with Lithium Ion cells, there are generally protection circuits to prevent cell voltages from exceeding manufacturer recommended limits or excessive currents caused by over charging, and shorted cells. Figure 46 shows a Smart Battery pack implemented with the MAX1780 Advanced Smart Battery Pack Controller.
DISCHARGE
CHARGE
FUSABLE LINK
+
C
+3.3V
DIS SHDN SCL VDD SDA THERMAL SAFETY CIRCUIT GPIO GPIO
BATT
CHG B4P
D S
VDD
Li+
B3P
EEPROM SCLK SO SI CS BATT B1P
100% 80% 60% 40% 20%
Li+
MAX1780
B2P 2nd PROTECTION
VDD
Li+
HVO HVO HVO HVO HVO INT AGND
Li+ AIN BN
PUSH
t
RSENSE
Figure 46, Typical Smart Battery Pack Implemented With The MAX1780
104
Advanced Smart Battery Pack Controller
Instruction Set Summary
Each MAX1780 instruction is a 12-bit word comprised of an Opcode, which specifies the instruction type, and one or more operands that further specify the operation of the instruction. For byte-oriented instructions, "f" represents a file register designator and "d" represents a destination designator. The file register designator is used to specify which one of the file registers is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If "d" is '0', the result is placed in the "W" Register. If "d" is '1', the result is placed in the file register specified in the instruction. For bit-oriented instructions, "b" represents a bit field designator that selects the number of the bit affected by the operation, while "f" represents the number of the file in which the bit is located. For literal and control operations, "k" represents an 8 or 9-bit constant or literal value. All instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles. One instruction cycle consists of four instruction oscillator clocks. Therefore, for a nominal instruction oscillator frequency of 3.5 MHz, the normal instruction execution time is approximately 1.14 s.
Mnemonic
ADDWF f, d ANDLW k ANDWF f, d BCF f, b BSF f, b BTFSC f, b BTFSS f, b CALL k CLRF f CLRW CLRWDT CLRTI COMF f, d DECF f, d DECFSZ f, d
Description
Adds the contents of the "W" register to contents of selected register. Results in "W" or f. ANDs the contents of the "W" register with literal (k) contained in instruction. Result in "W". ANDs the contents of the "W" register with contents of selected register. Result in "W" or f. Clears selected bit in selected register to 0. Sets selected bit in selected register to 1. Tests specified bit in selected register. Skips the next instruction if bit tested is clear (0). Tests specified bit in selected register. Skips the next instruction if bit tested is set (1). Call subroutine at specified starting address (k). Clears selected register to 0. Clears "W" register to 0. Clear Watchdog Timer (reset to 0). Also resets the WDT prescaler. Clear Watchdog Timer interrupt latch(reset to 0). Complements selected register's contents (1's to 0's/0's to 1's). Result in "W" or f. Decrements the selected register. Decrementing 0x00 results in 0xff. Result in "W" or f. Decrements specified register. Skips next instruction if register contents = 0. Result in "W" or f. The FREE instruction is used to write to the Program RAM and to the Interrupt Configuration Register. The instruction's specific action depends on the contents of FSR bits 5 and 6. Go to specified address (k). Increments the selected register. Incrementing 0xff results in 0x00. Result in "W" or f. Increments specified register. Skips next instruction if register contents = 0. Result in "W" or f. OR's contents of the "W" register with literal (k) contained in instruction. Result in "W". OR's contents of the "W" register with the contents of selected register. Result in "W" or f. Moves a copy of the selected register's contents into "W" or f.
Cycles
1 1 1 1 1 1(2) 1(2) 2 1 1 1 1 1 1 1(2)
Encoding
0001 11df ffff 1110 kkkk kkkk 0001 01df ffff 0100 bbbf ffff 0101 bbbf ffff 0110 bbbf ffff 0111 bbbf ffff 1001 kkkk kkkk 0000 011f ffff 0000 0100 0000 0000 0000 0100 0000 0001 0000 0010 01df ffff 0000 11df ffff 0010 11df ffff
Status
C, DC, Z Z Z None None None None None Z Z None None Z Z None
Notes
FREE GOTO k INCF f, d INCFSZ f, d IORLW k IORWF f, d MOVF f, d
1 2 1 1(2) 1 1 1
0000 0000 0001
None None Z None Z Z Z
101k kkkk kkkk 0010 10df ffff 0011 11df ffff 1101 kkkk kkkk 0001 00df ffff 0010 00df ffff
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Advanced Smart Battery Pack Controller
MOVLW k MOVWF f NOP OPTION RETFIE RETLW k RETURN RLF f, d RRF f, d SLEEP Loads the "W" register with literal (k). Moves a copy of the "W" register's contents into selected register. Do nothing for one instruction cycle. Load OPTION register with the contents of the "W" register. Return from Interrupt. The "W" register is unaffected and INTOFF flag bit is cleared. Return from subroutine. Load the "W" register with literal (k). Return from subroutine. The "W" register and INTOFF flag bit are unaffected. Rotates bits in selected register one position to the left. Bits rotate through the CARRY flag. Result in "W" or f. Rotates bits in selected register one position to the right. Bits rotate through the CARRY flag. Result in "W" or f. Shuts down C core (instruction oscillator) to reduce power consumption. Wake up via Reset, Watchdog Timer, or an external Interrupt. Subtracts the contents of the "W" register from the contents of selected register by 2's complement arithmetic. Results in "W" or f. Exchanges the upper and lower nibbles (4 bits) of the selected register. Result in "W" or f. Loads the selected Port (A, B, or C) register with the contents of the "W" register. XORs the contents of the "W" register with literal (k) contained in instruction. Result in "W". XORs the contents of the "W" register with the contents of selected register. Result in "W" or f. 1 1 1 1 2 2 2 1 1 1
1100 kkkk kkkk 0000 001f ffff 0000 0000 0000 0000 0000 0010 0000 0000 1001 1000 kkkk kkkk 0000 0000 1000 0011 01df ffff 0011 00df ffff
None None None None INTOFF None None C C INTOFF, INTWDT C, DC, Z None None Z Z
0000 0000 0011
SUBWF f, d SWAPF f, d TRIS f XORLW k XORWF f, d
1 1 1 1 1
0000 10df ffff
0011 10df ffff 0000 0000 0fff 1111 kkkk kkkk 0001 10df ffff
Legend: b = Bit Address d = Destination with "0" to "W" Register and "1" to File Register f = 5-bit File Register Address k = 8-bit Literal Value
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Advanced Smart Battery Pack Controller
Errata
Although all the issues listed here are expecte d to be addressed in future revisions of the MAX1780, care should be used to evaluate the implications of these issues in any specific design. The MAX1780 parts you have received conform functionally to this data sheet, except for the following issues.
1. ODO/OCO Section:
When the MAX1780 comes out of POR, the charge and discharge MOSFET drivers are asserted low.
Impact:
Cells are connected to the load before their voltages can be determined. In normal operation the MAX1780 will load program code from an external E2PROM after POR, and begin measuring the individual cell voltages within a few milliseconds. If the MAX1780 is unable to communicate with the external E2PROM, the voltage measurements will not be made. In such a case, the battery pack will then have to rely on an external second level protection element for safeguard against over voltage on cells.
Solution/Workaround:
Hardware change is required.
2. ODI/OCI Comparators:
When turning the protection MOSFETS ON (powering up the ODI/OCI comparators) in software, the comparators don't power up in a controlled manner.
Impact:
Spurious overcharge and discharge interrupts can occur.
Solution/Workaround:
A software workaround is currently used to minimize the effects of the problem. See the "Using Software To Control The Protection MOSFETs" section for an overview of the software workaround.
3. SPI Interface:
Over the full range of temperature and voltage, the MAX1780 may clock data into the SI pin up to 40ns too early for a 5MHz serial EEPROM.
Impact:
The MAX1780 does not meet SI setup and hold timing requirements for a 5MHz serial EEPROM.
Solution/Workaround:
A hardware change is required to guarantee SPI communications at 5MHz. There is no timing problem when operating the SPI interface at the slower SCLK speed.
4. SMBus Interface:
The MAX1780 SMBus Master Interface may have some difficulty communicating in a multi-master environment. There are three areas of concern: a. The MAX1780 does not implement the Tlow:sext and Tlow:mext timeouts. b. The MAX1780 does not perform SCL clock synchronization. c. The MAX1780 does not do bit-by-bit data arbitration.
Impact:
Master communications in a multi-master environment may be unreliable.
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Advanced Smart Battery Pack Controller
Solution/Workaround:
Hardware changes are required to alleviate all three problems, however it is possible to implement the Tlow:sext and Tlow:mext timeouts in software. Byte-by-byte data arbitration can also be performed in software.
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